【FPGA】Visual Studio Code 使用Verilog语言用户代码片段分享

// An highlighted block
var foo = 'bar';{
	// Place your snippets for verilog here. Each snippet is defined under a snippet name and has a prefix, body and 
	// description. The prefix is what is used to trigger the snippet and the body will be expanded and inserted. Possible variables are:
	// $1, $2 for tab stops, $0 for the final cursor position, and ${1:label}, ${2:another} for placeholders. Placeholders with the 
	// same ids are connected.
	// Example:
	// "Print to console": {
	// 	"prefix": "log",
	// 	"body": [
	// 		"console.log('$1');",
	// 		"$2"
	// 	],
	// 	"description": "Log output to console"
	// }


		"Jsq": {
			"prefix": "Jsq(计数器)",
			"body": [
			"always @(posedge clk or negedge rst_n)begin "
			"   if(!rst_n)begin" 
			"		cnt <= 0;"
			"	end "
			"	else if(add_cnt)begin "
			"			if(end_cnt)begin "
			"				cnt <= 0;"
			"			end" 
			"			else begin "
			"				cnt <= cnt + 1;"
			"			end "
			"	end" 
			"   else  begin"
			"       cnt <= cnt;"
			"	end" 
			"end "
			""
			"assign add_cnt = ;"
			"assign end_cnt = add_cnt && cnt == ;"
			],
			"description": "counter"
	   }
	
	
	   "Tb": {
		   "prefix": "Tb(testbeenth)",
		   "body": [
			  "`timescale 1ns/1ns"
			  "				" 
			  "module module_name_tb();"
			  "//激励信号定义 "
			  "reg				tb_clk  	;"
			  "reg				tb_rst_n	;"
			  "reg				tb_din0		;"
			  "reg				tb_din1		;"
			  "reg				tb_din2		;"
			  "//输出信号定义	 "
			  "wire	[n:0]		tb_dout0	;"
			  "wire	[n:0]		tb_dout1    ;"
			  "									      "
			  "//时钟周期参数定义					        "
			  "	parameter		CLOCK_CYCLE = 20;    "
			  "									      "
			  "module_name u_madule_name(			      "
			  ".clk			(tb_clk			),			      "
			  ".rst_n		(tb_rst_n		),			      "
			  ".din0		(tb_din0		),			      "
			  ".din1		(tb_din1		),			      "
			  ".dout0		(tb_dout0		),			      "
			  ".dout1		(tb_dout1		)			      "
			  ");" 
			  "//产生时钟							       		"
			  "initial 		tb_clk = 1'b0;		       		"
			  "always #(CLOCK_CYCLE/2) tb_clk = ~tb_clk;  		"
			  "									       		"
			  "//产生激励							       		"
			  "initial  begin						       		"
			  "	tb_rst_n = 1'b1;								"
			  "	tb_din0 = 0;								"
			  "	#(CLOCK_CYCLE*2);				            "
			  "	tb_rst_n = 1'b0;							"
			  "	#(CLOCK_CYCLE*20);				            "
			  "	tb_rst_n = 1'b1;							"
			  "									       		"
			  "								       			"
			  "									       		"
			  "end 									       	"
			  "endmodule 									       	"
		   ],
		   "description": "Testbeench"
		}
	
		"Do": {
		   "prefix": "Do",
		   "body": [
		   "#tcl脚本  自动化仿真                         "                                      

		   "#创建工作库 名为work                       "
		   "vlib work                       "
		   "                                    "
		   "#映射工作库 work 到 work                   "
		   "vmap work work                           "
		   "   "
		   "#编译testbench文件                     "
		   "vlog key_led_tb.v                       "
		   "                                                    "
		   "#若要仿真IP核必须添加该文件                                 "
		   "#vlog altera_mf.v                                   "
		   "		                                                  "
		   "#编译被仿真文件                                                "
		   "#vlog ../rtl/key_led.v                                         "
		   "#vlog ../rtl/key_filter.v                                   "
		   "#vlog ../rtl/led.v                                          "
		   "                                                           "
		   "#对IP核进行仿真                                               "
		   "#vlog ../par/ipcore/pll.v                                    "
		   "                                                             "
		   "#指定仿真顶层                                                 "
		   "vsim -novopt work.key_led_tb"
		   "                                                            "
		   "#添加testbench顶层模块中的信号到波形窗
		   "add wave -position insertpoint sim:key_led_tb//*            "
		   "															"
		   "#表示让该tb_clk信号显示黄色									"
		   "#add wave -noupdate -color Yellow /follow_led_tb/tb_clk		"
		   "                                                             "
		   "#表示让div_coef信号用十进制tb_led来显示						   "
		   "#add wave -noupdate -radix decimal /follow_led_tb/tb_led     "
		   "                                                             "
		   "#运行2000个时间单位                                           "
		   "run 2000                                                     "
		   "                                                             "
		   "#一直仿真下去                                                 "
		   "#run -all                                                    "	
		   ],
	   "description": "Do"
		}
	//Light arc rabbit
		"Zhushi": {
		   "prefix": "Zhushi(注释模板)",
		   "body": [
		   "/**************************************功能介绍***********************************"
		   "MY own style good!!!   ♬♩♫♪☻(●´∀｀●）♪♫♩♬"
		   "//--------------------------------------------------------------------------------"
		   "Copyright		:			"  
		   "//--------------------------------------------------------------------------------"                                                                              
		   "Date     		:			"                                                     
		   "//--------------------------------------------------------------------------------"                            
		   "Author   		:Light arc rabbit-->lcy			( ᵒ̴̶̷̤໐ᵒ̴̶̷̤ )"                                                              
		   "//--------------------------------------------------------------------------------" 
		   "Tool version 	:"
		   "//--------------------------------------------------------------------------------"                  
		   "Version  		:			"
		   "//--------------------------------------------------------------------------------"
		   "Description		:		"
		   "//--------------------------------------------------------------------------------"
		   "*********************************************************************************/"
		   ],
	   "description": "Zhushi"
		}

		"tb(rst_n,clk)":{
			"prefix":"tb(rst_n,clk)",
			"body": [
				"//->Module Information"
				"//author:Light arc rabbit"
				"//date:2022/12/04"
				""
				"`timescale 1ns/1ns" 
				"module tb();"  
				""
				"wire					clk_50m		;"
				"wire					clk_100m	;"
				"wire					rst_n		;"
				""
				""
				""
				"tb_clk_gen tb_clk_gen_inst"
				"("
				"		/*output              */.clk_50m     (clk_50m	),"
				"		/*output              */.clk_100m    (clk_100m	),"
				"		/*output              */.rst_n       (rst_n		) "
				");"
				""
				"endmodule"     
				""
				""
				"//Obtain the simulation clock reset signal"     
				"module tb_clk_gen("
				"		output              clk_50m     ,"
				"		output              clk_100m    ,"
				"		output              rst_n        "
				");"
				"" 
				"reg				tb_clk_50m  	;"
				"reg				tb_clk_100m  	;"
				"reg				tb_rst_n	    ;"										  
				""					        
				"parameter		CLOCK_CYCLE50  = 20;"
				"parameter		CLOCK_CYCLE100 = 10;"    
				""							       		
				"initial 		tb_clk_50m  = 1'b0;"	
				"initial 		tb_clk_100m = 1'b0;"	       		
				"always #(CLOCK_CYCLE50/2) tb_clk_50m = ~tb_clk_50m;"  		
				"always #(CLOCK_CYCLE100/2) tb_clk_100m = ~tb_clk_100m;"  
				""																			       		
				"initial  begin"			
				"	tb_rst_n = 1'b1     ;"
				"	#(CLOCK_CYCLE50*2)  ;"
				"	tb_rst_n = 1'b0     ;"
				"	#(CLOCK_CYCLE50*10) ;"
				"	tb_rst_n = 1'b1     ;"
				"end" 									       	
				
				"assign clk_50m  = tb_clk_50m  ;"    
				"assign clk_100m = tb_clk_100m ;"    
				"assign rst_n    = tb_rst_n	  ;"
				""
				"endmodule" 
					],
			"description": "tb(rst_n,clk)"
		}

		"log2":{
			"prefix":"log2",
			"body": [
				"function integer funclog2;"
				"input   integer value;"
				"begin"
				"	value = value-1;"
				"	for (funclog2 = 0; value>0; funclog2 = funclog2+1) begin"
				"		value = value>>1;"
				"	end"
				"end"
				""
			    "endfunction"
					],
			"description": "log2"
		}

		"TOP module": {
			"prefix": "TOP (顶层模块)",
			"body": [
				"module top_module_name"
				"("
				"input						i_clk					,"
				"input						i_rst_n					,"
				");"
				""
				"//parameters"
				""
				"//signal"
				""
				""
				"endmodule"
			],
			"description": "TOP module"
	   }

	   "module": {
		"prefix": "module",
		"body": [
			"module top_module_name"
			"("
			"input						i_clk					,"
			"input						i_rst_n					,"
			");"
			""
			"//parameters"
			""
			"//signal"
			""
			""
			"endmodule"
		],
		"description": "module"
   }

   "shixu": {
	"prefix": "shixu时序逻辑",
	"body": [
		"always @(posedge i_clk )begin" 
			"    if()begin" 
			""        
			"    end" 
			"    else begin" 
			""        
			"    end" 
			"end"
	],
	"description": "shixu"
}

	"shixu1": {
		"prefix": "shixu(rst_n)时序逻辑",
		"body": [
			"always @(posedge i_clk or negedge i_rst_n)begin" 
			"    if(!i_rst_n)begin"
			""       
			"    end" 
			"    else if()begin" 
			""        
			"    end" 
			"    else begin" 
			""        
			"    end" 
			"end"
		],
		"description": "shixu1"
}

"zuhe": {
	"prefix": "zuhe组合逻辑",
	"body": [
		"always @(*)begin" 
		"    if()begin" 
		""        
		"    end" 
		"    else begin" 
		""        
		"    end" 
		"end"
	],
	"description": "zuhe"
}

}