一、if-else语句
`timescale 1ns / 1ps
module led_test
(
sys_clk, // system clock 50Mhz on board
rst_n, // reset ,low active
sel1,
sel2,
sel3,
z
);
input sys_clk;
input rst_n;
input sel1;
input sel2;
input sel3;
output reg [7:0] z;
reg [7:0] a = 'd1;
reg [7:0] b = 'd2;
reg [7:0] c = 'd4;
always@(*) begin
z = 'd8;
if(sel1)
z = a;
else if(sel2)
z = b;
else if(sel3)
z = c;
end
endmodule
`timescale 1ns / 1ps
module vtf_led_test;
// Inputs
reg sys_clk;
reg rst_n;
// Outputs
reg sel1;
reg sel2;
reg sel3;
wire [7:0] z;
led_test led_test1 (
.sys_clk(sys_clk),
.rst_n(rst_n),
.sel1 (sel1),
.sel2 (sel2),
.sel3 (sel3),
.z (z)
);
initial begin
// Initialize Inputs
sys_clk = 0;
rst_n = 0;
sel1 =0;
sel2 =0;
sel3 =0;
// Wait 100 ns for global reset to finish
#1000;
rst_n = 1;
// Add stimulus here
#2000;
sel1 =1;
sel2 =0;
sel3 =0;
#1000;
sel1 =0;
#2000;
sel1 =0;
sel2 =1;
sel3 =0;
#1000;
sel2 =0;
#2000;
sel1 =0;
sel2 =0;
sel3 =1;
#1000;
sel3 =0;
#2000;
sel1 =1;
sel2 =1;
sel3 =1;
#2000;
$stop;
end
always #10 sys_clk = ~ sys_clk; //20ns一个周期,产生50MHz时钟源
endmodule
仿真图:
RTL视图:
总结:if-else语句,靠前的if优先级高。
二、多if语句
`timescale 1ns / 1ps
module led_test
(
sys_clk, // system clock 50Mhz on board
rst_n, // reset ,low active
sel1,
sel2,
sel3,
z
);
input sys_clk;
input rst_n;
input sel1;
input sel2;
input sel3;
output reg [7:0] z;
reg [7:0] a = 'd1;
reg [7:0] b = 'd2;
reg [7:0] c = 'd4;
always@(*) begin
z = 'd8;
if(sel1)
z = a;
if(sel2)
z = b;
if(sel3)
z = c;
end
endmodule
仿真图:
RTL视图:
总结:多if语句语句,靠后的if优先级高。
利用多if语句的这个条件,可以用来调整电路结构,若是某个控制信号来得较晚,则可以使用多if语句,将此信号的优先级调高。
但是,在设计中尽量采用单if语句,单if语句更简单,不容易出错。