Verilog HDL 按键消抖模块

因为常用就贴在这里随时调用。

module debounce(clk,rst,key_in,key_out);
    input clk;
    input [0:0]rst;
    input [0:0]key_in;
    output key_out;
    
    reg [0:0]key_out;

    localparam frequence = 50_000_000;//这里填时钟信号的频率
    localparam _20ms = 0.02 * frequence;

    reg [0:0]key_cnt;
    reg [31:0] cnt;

    always @(posedge clk or negedge rst) begin
        if(rst == 0) begin
            key_cnt <= 0;
            cnt <= 0;
            key_out <= 0;
        end
        else begin
            if(key_cnt == 0 && key_out != key_in)
                key_cnt <= 1;
            else if(cnt == _20ms - 1) begin
                key_cnt <= 0;
                key_out <= key_in;
            end

            if(key_cnt)
                cnt <= cnt + 1'b1;
            else
                cnt <= 0;
        end
    end

endmodule