HDLbits--lemmings4

在前一题基础上修改，只有当fall状态才能转化为dead状态 dead状态下输出全为0，直到复位。 

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    
    
    parameter left=0,right=1,fall_l=2,fall_r=3,dig_l=4,dig_r=5,dead=6;
    reg[2:0] state,next_state;
    int count;
    
    //state change logic
    always @(*)
        begin
            case(state)
                left:
                    next_state<=(ground)? (dig?dig_l:(bump_left?right:left)):fall_l;
                right:
                    next_state<=ground? (dig?dig_r: (bump_right?left:right)):fall_r;
                fall_r:
                    next_state<=ground? count>20?dead:right:fall_r;
                fall_l:
                    next_state<=ground?count>20?dead:left:fall_l;
                dig_l:
                    next_state<=ground? dig_l:fall_l;
                dig_r:
                    next_state<=ground? dig_r:fall_r;
                dead:
                    next_state<=dead;
            endcase
        end
    
    //
    always@(posedge clk,posedge areset)
        begin
            if(areset)
                state<= left;
            else
                state<=next_state;
        end
    
    always@(posedge clk)
        begin
            if(state==fall_r||state==fall_l)
                count=count+1;
            else
                count=0;
        end
            
    
    //output logic
    assign walk_left=(state==left);
    assign walk_right=(state==right);
    assign digging= (state==dig_r|| state==dig_l);
    assign aaah=(state==fall_r ||state==fall_l);
                    

endmodule

结果在580秒时错误，walkleft/right仍有输出

修改：在计数时序逻辑块内吧state改成next-state

结果正确： 

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    
    
    parameter left=0,right=1,fall_l=2,fall_r=3,dig_l=4,dig_r=5,dead=6;
    reg[2:0] state,next_state;
    int count;
    
    //state change logic
    always @(*)
        begin
            case(state)
                left:
                    next_state<=(ground)? (dig?dig_l:(bump_left?right:left)):fall_l;
                right:
                    next_state<=ground? (dig?dig_r: (bump_right?left:right)):fall_r;
                fall_r:
                    next_state<=ground? count>20?dead:right:fall_r;
                fall_l:
                    next_state<=ground?count>20?dead:left:fall_l;
                dig_l:
                    next_state<=ground? dig_l:fall_l;
                dig_r:
                    next_state<=ground? dig_r:fall_r;
                dead:
                    next_state<=dead;
            endcase
        end
    
    //
    always@(posedge clk,posedge areset)
        begin
            if(areset)
                state<= left;
            else
                state<=next_state;
        end
    
    always@(posedge clk)
        begin
            if(next_state==fall_r||next_state==fall_l)
                count=count+1;
            else
                count=0;
        end
            
    
    //output logic
    assign walk_left=(state==left);
    assign walk_right=(state==right);
    assign digging= (state==dig_r|| state==dig_l);
    assign aaah=(state==fall_r ||state==fall_l);
                    

endmodule

反思：仍然不清楚组合逻辑和时序逻辑，最时序没有搞清楚

有人指出：时序逻辑内参考状态为 next-state 组合逻辑内参考状态为state。

参考链接: (11条消息) HDLBits刷题记录——FSM Lemmings4_Candy_579的博客-CSDN博客