基于quartus ii求补码的VHDL程序（输入是带符号的4位二进制数）

代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.STD_LOGIC_ARITH.all;
entity complement is
port(
	a:in std_logic_vector(3 downto 0);
	sout:out STD_LOGIC_VECTOR(3 DOWNTO 0);
	clk:in std_logic;
	cout:out bit);
	END complement;
architecture ONE of complement is
begin
process(clk)
variable temp: std_logic_vector(3 downto 0);
begin
if clk'event and clk = '1' then --上升沿 
if a(3)='1' then 
if a(2 downto 0)="000" then cout<='1';
else cout<='0';
end if;
temp:=a XOR "0111";--异或求反
temp:=CONV_STD_LOGIC_VECTOR(CONV_INTEGER(temp)+1,4);--temp转换成整数加1后再转换回来	
else
temp:= a;
end if;
end if;
sout <= temp;
end process;
end ONE;