HDLBits Karnaugh Map to circuit

Exams/ece241 2013 q2

SOP :最小项之和: 化简卡诺图中的1

POS:最大项之积：化简卡诺图中的0后取反

module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
);
    assign out_sop = c&d | ~a&~b&c;
    assign out_pos = c & (~a | d) & (~b | d);

endmodule

Exams/m2014 q3

module top_module (
    input [4:1] x,
    output f );
    
    assign f = ~x[1]&x[3] | x[2]&x[4];

endmodule

Exams/2012 q1g

module top_module (
    input [4:1] x,
    output f
);
    
    assign f = ~x[1]&x[3] | ~x[2]&~x[4] | x[2]&x[3]&x[4];

endmodule

Exams/ece241 2014 q3

module top_module (
    input c,
    input d,
    output [3:0] mux_in
);
    
    assign mux_in[0] = (c|d);
    assign mux_in[1] = 0;
    assign mux_in[2] = ~d;
    assign mux_in[3] = c&d;

endmodule