「HDLBits题解」Karnaugh Map to Circuit

本专栏的目的是分享可以通过HDLBits仿真的Verilog代码 以提供参考 各位可同时参考我的代码和官方题解代码 或许会有所收益

相关资料：卡诺图化简法-CSDN博客

---

题目链接：Kmap1 - HDLBits 

module top_module(
    input a,
    input b,
    input c,
    output out  
);
    assign out = a & ~b | c & ~b | b ;

endmodule

---

题目链接：Kmap2 - HDLBits

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  
);
    assign out = (~a & ~c & ~d) | (~a & ~b & ~c) | (a & ~b & ~c) | (a & c & d) | (~a & b & c) | (~a & c & ~d);

endmodule

---

题目链接：Kmap3 - HDLBits

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  
);
    assign out = (a & ~c & ~d) | (a & c) | (~a & ~b & c);

endmodule

---

题目链接：Kmap4 - HDLBits

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  
);
    assign out = a ^ b ^ c ^ d;

endmodule

---

题目链接：Exams/ece241 2013 q2 - HDLBits 

module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
); 
    assign out_sop = (~a & ~b & c) | (b & c & d) | (a & c & d);
    assign out_pos = c &(~a | d) & (~b | d);

endmodule

---

题目链接：Exams/m2014 q3 - HDLBits 

module top_module (
    input [4:1] x, 
    output f 
);
    assign f = (~x[1] & x[3]) | (x[2] & x[4]) ;

endmodule

---

题目链接：Exams/2012 q1g - HDLBits

module top_module (
    input [4:1] x,
    output f
); 
    wire x1, x2, x3, x4 ; 

    assign x1 = x[1];
    assign x2 = x[2];
    assign x3 = x[3];
    assign x4 = x[4];

    assign f = (~x1 & x3) | (~x1 & ~x2 & ~x4) | (x2 & x3 & x4) | (x1 & ~x2 & ~x4) ;

endmodule

---

题目链接：Exams/ece241 2014 q3 - HDLBits

module top_module (
    input c,
    input d,
    output [3:0] mux_in
); 
    assign mux_in[0] = c | d ; 
    assign mux_in[1] = 0 ; 
    assign mux_in[2] = ~d ; 
    assign mux_in[3] = c & d ;
    
endmodule