FPGA

XC7A35T-1CSG324C FPGA，BIT，vivado+modelsim,verilog

As a green hand, I met tons of difficulty when I started using modelsim to write the verilog code, so I code faced to CSDN, but, there are still plenty of problems, while for FPGA, the code is not important, but the vivado is.
I don’t know how to debug with modelsim, and our teacher told us that we need to use modelsim or vivado to simulate, and code our own debug code: testbench, these all code is very easy, but it’s not easy to write it right, to make your code run successfully in the stage of simulation, you may have caution about the message col, very important, because even you copy the code from CSDN or from me, you still can’t promise it’s useful, so here mention please:if you don’t know what’s the error or warning means, remember search for it in baidu or google, and remember, even you can run it yet it might be wrong when you synthesis or implementation.
verilog is not friendly to the beginner, but never mind, you have to try all the problem, then you will know how to design the circuit, now let’s begin:
first, maybe you will meet your “hello world” of verilog, a easy circuit, a encoder or a decoder. but I bet, even you are proficient about code, you will still make some stupid mistakes, that’s not important, and I will show you some mistakes of mine code:
I design the first task: 8-3 priority encoder, I got the code from CSDN, the writer gave the code only, but he didn’t assure his procedure is right, I spent half a day knowing how to change it right. the origin is here(got from: MasterZLee)
testbench:

`timescale 1ns/1ns	
module tb;          
   reg [7:0] din;
  wire [2:0] dout;   

  initial begin
  	               din = 8'b00000000 ;
      forever #5   din = din+1;	
  end
				 

YOUXIAN83 u_YOUXIAN83

function:

module YOUXIAN83 ( din,dout );
 input  [7:0]  din;
 output [0:2] dout;
    reg [2:0] dout;
always @( * )
  begin
	       if (din==8'b???????0) dout=3'b000;
	  else if (din==8'b??????01) dout=3'b100;
	  else if (din==8'b?????011) dout=3'b010;
   	else if (din==8'b????0111) dout=3'b110;
   	else if (din==8'b???01111) dout=3'b001;
   	else if (din==8'b??011111) dout=3'b101;
	  else if (din==8'b?0111111) dout=3'b011;
	  else if (din==8'b01111111) dout=3'b111;
                          else dout=3'b000;
  end
endmodule

I think his thought is right, and I know his code is wrong in somewhere, yet I don’t know how to correct it. the core part of the code is these else if, while it’s judgement need to be modified, you can’t write ? in the sentence of if, but you can try to achieve his thought: while the last bit is 0, you don’t need to judge others, the dout is 3’b000(there is something mismatch the teachers demands). so we can write our own code in this train of thought.
And because our verilog is facing the circuit, actually we can code as designing a circuit, we have tools like “&、|、~、+、-”， no more “*,/”. you can realize the former judgement with "&、|、~ "only.
For me, I can’t run a simple encoder even I copy the code, so I suggest you to copy,copy,copy, until you have a good commend of verilog and vivado, or you will meet countless bugs.
Also, you need to have a intact process of running vivado:
build a project(choose the right board,the series of the title)->get the file.v from modelsim or vivado->debug and simulation(use your test bench)->synthesis->implementation->I/O planing->generate->open the hardware manager
and if have spare time, I will record a video in the next issue.if you want to code in vivado, click the name of the file, double click.