- module uart_tx(
- rst,
- clk,
- baud_set, //波特率設置
- din, //欲發送的數據
- tx, //發送數據
- done //發送結束時done為1
- );
- input rst,clk;
- input [7:0] din;
- input [2:0] baud_set;
- output tx;
- output done;
- reg [12:0] div_cnt;
- reg [3:0] bps_cnt;
- reg [7:0] reg0_din;
- reg [7:0] reg1_din;
- reg tx;
- reg en;
- reg [12:0] bps_DR; //分频计数最大值
- //=============================================
- // 狀態機
- //=============================================
- parameter trans = 1'b0, //發送數據
- finish = 1'b1; //發送結束
- reg present_state, next_state;
- always@(posedge clk or negedge rst)
- begin
- if(!rst) present_state <= trans;
- else present_state <= next_state;
- end
- always@(bps_cnt or div_cnt or present_state)
- begin
- case(present_state)
- trans : if(div_cnt == 13'd5207 && bps_cnt ==