- //系統f=50MHz, T=20ns
- //9ms=9x10^-3, (9x10^-3)/(20x10^-9)=450000 (取可接受誤差為正負10%)
- //4.5ms=4.5x10^-3, (4.5x10^-3)/(20x10^-9)=225000 (取可接受誤差為正負10%)
- //560μs =560x10^-6, (560x10^-6)/(20x10^-9)=28000 (取可接受誤差為正負10%)
- //1690μs =1690x10^-6, (1690x10^-6)/(20x10^-9)=84500 (取可接受誤差為正負10%)
- module Infrared(
- clk,
- rst,
- ir, //紅外線輸入
- addr, //器件地址
- data, //數據
- done //傳輸結束標誌信號
- );
- input clk;
- input rst;
- input ir;
- output [15:0] addr;
- output [15:0] data;
- output done;
- reg ir_reg0;
- reg ir_reg1;
- reg ir_tmp0;
- reg ir_tmp1;
- wire nedge;
- wire pedge;
- reg [18:0] T9ms_cnt;
- reg [17:0] T4_5ms_cnt;
- reg T9ms_en;
- reg T4_5ms_en;
- reg [16:0] cnt;
- reg [5:0] n_cnt;
- reg [31:0] data_tmp;
- //================================================
- //狀態機
- //================================================
- parameter [5:0] Idle0 = 6'b00_0001, //空閒態
- T9ms = 6'b00_0010, //9ms
- T4_5ms = 6'b00_0100, //4.5ms
- Trans = 6'b00_1000, //傳輸地址和數據
- Stop = 6'b01_0000, //停止
- Idle1 = 6'b10_0001; //空閒態
- reg [5:0] present_state, next_state;
- always@(posedge clk or negedge rst)
- begin
- if(!rst) present_state <= Idle0;
- else present_state <= next_state;
- end
- always@(*)
- begin
- case(present_state)
- Idle0 : if(nedge)
- next_state = T9ms;
- else
- next_state = Idle0;
- T9ms : if(pedge && (T9ms_cnt >= 19'd405000 && T9ms_cnt <= 19'd495000))
- next_state = T4_5ms;
- else </
IR 紅外線遙控解碼
最新推荐文章于 2022-11-28 23:04:48 发布
该博客详细介绍了红外遥控解码的过程,包括9ms和4.5ms脉冲的计数与检测,以及状态机的实现。通过Verilog代码展示了如何识别红外信号并解析出器件地址和数据,最后通过测试程序验证了解码模块的功能。
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