任务要求(注:已经上板验证过)
使LED呈现流水和呼吸的效果。
板卡介绍以及所用模块
开发板是正点原子的XCZU2EG,led使用的是扩展模块上的LED。
代码实现
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/04/27 18:42:54
// Design Name:
// Module Name: breath_led
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module breath_led(
input clk ,
input rst_n ,
output [ 7: 0] led
);
parameter t0 = 999 ;
parameter t1 = 99 ;
parameter t2 = 99 ;
reg [ 31: 0] cnt0,cnt1,cnt2 ;
always@ (posedge clk or negedge rst_n)
if (!rst_n)
cnt0 <= 0;
else if (cnt0 == t0)
cnt0 <= 0;
else
cnt0 <= cnt0 + 1;
always@ (posedge clk or negedge rst_n)
if (!rst_n)
cnt1 <= 0;
else if (cnt1 == t1 && cnt0 == t0)
cnt1 <= 0;
else if (cnt0 == t0)
cnt1 <= cnt1 + 1;
always@ (posedge clk or negedge rst_n)
if (!rst_n)
cnt2 <= 0;
else if ( cnt2 == t2 && cnt1 == t1 && cnt0 == t0)
cnt2 <= 0;
else if ( cnt1 == t1 && cnt0 == t0)
cnt2 <= cnt2 + 1;
reg flag ;
always@ (posedge clk or negedge rst_n)
if (!rst_n)
flag <= 0;
else if ( cnt2 == t2 && cnt1 == t1 && cnt0 == t0)
flag <= ~flag;
else
flag <= flag;
reg flag_d ;
always@ (posedge clk or negedge rst_n)
if (!rst_n)
flag_d <= 0;
else
flag_d <= flag;
wire n_dge ;
assign n_dge = flag_d & (!flag);
reg [ 2: 0] led_ctrl ;
always @ (posedge clk or negedge rst_n)
if (!rst_n)
led_ctrl <= 0;
else if (n_dge)
led_ctrl <= led_ctrl + 1;
else
led_ctrl <= led_ctrl;
reg led_d ;
always @ (posedge clk or negedge rst_n)
if (!rst_n)
led_d <= 0;
else if ((cnt1 <= cnt2 && flag) || (cnt1 >= cnt2 && !flag))
led_d <= 1;
else
led_d <= 0;
reg [ 7: 0] led_dd ;
always @ (posedge clk or negedge rst_n)
if (!rst_n)
led_dd <= 8'b00000000;
else
case(led_ctrl)
3'b000:led_dd<= {led_d,7'b0000000};
3'b001:led_dd<= {1'b0,led_d,6'b000000};
3'b010:led_dd<= {2'b00,led_d,5'b00000};
3'b011:led_dd<= {3'b000,led_d,4'b0000};
3'b100:led_dd<= {4'b0000,led_d,3'b000};
3'b101:led_dd<= {5'b00000,led_d,2'b00};
3'b110:led_dd<= {6'b000000,led_d,1'b0};
3'b111:led_dd<= {7'b0000000,led_d};
endcase
assign led = led_dd;
endmodule
`timescale 1ns / 1ps // // Company: // Engineer: // // Create Date: 2024/04/27 20:33:33 // Design Name: // Module Name: top // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // // module top( input sys_clk_p , input sys_clk_n , input rst_n , output [ 7: 0] led ); wire clk ; IBUFDS IBUFDS_inst ( .O (clk ),// 1-bit output: Buffer output .I (sys_clk_p ),// 1-bit input: Diff_p buffer input (connect directly to top-level port) .IB (sys_clk_n ) // 1-bit input: Diff_n buffer input (connect directly to top-level port) ); breath_led #( .t0 (99 ), .t1 (1299 ), .t2 (1299 ) ) u_breath_led( .clk (clk ), .rst_n (rst_n ), .led (led ) ); endmodule