Verilog 练习 串口数据发送

 

 代码如下

//2021-11-5
//串口发送模块；
`timescale 1ns/10ps
module UART_TXer(
				clk,
				res,
				data_in,
				en_data_in,
				TX,
				rdy
				);
input			clk;
input			res;
input[7:0]		data_in;//数据；
input			en_data_in;//发送使能；
output			TX;
output			rdy;//空闲标志，0表示空闲；

reg				state;//主状态机寄存器；
reg[9:0]		send_buf;//发送寄存器；
assign			TX=send_buf[0];

reg[9:0]		send_flag;//用于判断右移结束；

reg[12:0]		con;//用于计算比特周期；
reg				rdy;

always@(posedge clk or negedge res)
if(~res) begin
	state<=0;send_buf<=1;con<=0;send_flag<=10'b10_0000_0000;
	rdy<=0;
end 
else begin
	case(state) 
	0://等待使能信号；
	begin
		if(en_data_in) begin 
			send_buf<={1'b1,data_in,1'b0};
			send_flag<=10'b10_0000_0000;
			rdy<=1;
			state<=1;
		
		end 
		
	end 
	1://
	begin
		if(con==5000-1) begin
			con<=0;
		
		end 
		else begin
			con<=con+1;
		end 
		
		if(con==5000-1) begin
			send_buf[8:0]<=send_buf[9:1];
			send_flag[8:0]<=send_flag[9:1];
			
		end 
		
		if(send_flag[0]) begin
			rdy<=0;
			state<=0;
		end 
	
	end 
	
	
	endcase

end 

endmodule


//----testbench of UART_TXer----
module UART_TXer_tb;
reg					clk,res;
reg[7:0]			data_in;
reg					en_data_in;
wire				TX;
wire				rdy;

UART_TXer UART_TXer(
					clk,
					res,
					data_in,
					en_data_in,
					TX,
					rdy
					);

initial begin
				clk<=0;res<=0;data_in<=8'h0a;en_data_in<=0;
	#17			res<=1;
	#30			en_data_in<=1;
	#10			en_data_in<=0;
	#2000000	$stop;
end 

always #5 clk<=~clk;

endmodule

仿真结果如下

 data_in<=8'h7f的仿真结果如下

https://www.bilibili.com/video/BV1hX4y137Ph?p=9&spm_id_from=pageDriver