Verilog 练习 二选一逻辑和四选一逻辑

 代码如下

//2021-11-2
//二选一逻辑设计
`timescale 1ns/10ps
module fn_sw(y,a,b,sel);
output	y;
input	a,b,sel;

assign	y=sel?(a^b):(a&b); //如果sel为1，执行：前面的逻辑运算，否则执行后面的

endmodule


//------testbench of fn_sw-------
module fn_sw_tb;
reg a,b,sel;
wire y;

fn_sw fn_sw(.y(y),.a(a),.b(b),.sel(sel));

initial begin
		a<=0;b<=0;sel<=0;
	#10	a<=0;b<=0;sel<=1;
	#10	a<=0;b<=1;sel<=0;
	#10	a<=0;b<=1;sel<=1;
	#10	a<=1;b<=0;sel<=0;
	#10	a<=1;b<=0;sel<=1;
	#10	a<=1;b<=1;sel<=0;
	#10	a<=1;b<=1;sel<=1;
	#10	$stop;
end 

endmodule

仿真结果如下

也可以用always语句块实现二选一逻辑 

代码如下

//2021-11-2
//二选一逻辑设计
`timescale 1ns/10ps
module fn_sw(y,a,b,sel);
output	y;
input	a,b,sel;
reg y;

always@(a or b or sel) begin
	if(sel==1) begin
		y=a^b;
	end 
	else begin
		y=a&b;
	end 
end 


endmodule


//------testbench of fn_sw-------
module fn_sw_tb;
reg a,b,sel;
wire y;

fn_sw fn_sw(.y(y),.a(a),.b(b),.sel(sel));

initial begin
		a<=0;b<=0;sel<=0;
	#10	a<=0;b<=0;sel<=1;
	#10	a<=0;b<=1;sel<=0;
	#10	a<=0;b<=1;sel<=1;
	#10	a<=1;b<=0;sel<=0;
	#10	a<=1;b<=0;sel<=1;
	#10	a<=1;b<=1;sel<=0;
	#10	a<=1;b<=1;sel<=1;
	#10	$stop;
end 

endmodule

仿真结果如下

 当sel扩展为2位时，变为四选一逻辑

 代码如下

//2021-11-2
//四选一逻辑
`timescale 1ns/10ps
module fn_sw_4(y,a,b,sel);
output y;
input a,b;
input[1:0] sel;
reg y;

always@(a or b or sel) begin
	case(sel)
	2'b00:y<=a&b;
	2'b01:y<=a|b;
	2'b10:y<=a^b;
	2'b11:y<=~(a^b);
	endcase
end 

endmodule 


//-----testbench of fn_sw_4----
module fn_sw_4_tb;
reg[3:0] absel;
wire y;

fn_sw_4 fn_sw_4(.y(y),.a(absel[0]),.b(absel[1]),.sel(absel[3:2]));

initial begin
	absel<=0;
	#200 $stop;
end 

always#10 absel<=absel+1;

endmodule

仿真结果如下

 这是视频教学https://www.bilibili.com/video/BV1hX4y137Ph?p=2&spm_id_from=pageDriver