VHDL交通信号灯

library ieee;
use ieee.std_logic_1164.all;

entity decode is
   port(input: in std_logic_vector(4 downto 0);
		out_h,out_l:out std_logic_vector(3 downto 0));
end decode;

architecture bhv of decode is
begin
	process(input)
	begin
	case input is
		when "00000"=>out_h<="0000";out_l<="0000";
		when "00001"=>out_h<="0000";out_l<="0001";
		when "00010"=>out_h<="0000";out_l<="0010";
		when "00011"=>out_h<="0000";out_l<="0011";
		when "00100"=>out_h<="0000";out_l<="0100";
		when "00101"=>out_h<="0000";out_l<="0101";
		when "00110"=>out_h<="0000";out_l<="0110";
		when "00111"=>out_h<="0000";out_l<="0111";
		when "01000"=>out_h<="0000";out_l<="1000";
		when "01001"=>out_h<="0000";out_l<="1001";
		when "01010"=>out_h<="0001";out_l<="0000";
		when "01011"=>out_h<="0001";out_l<="0001";
		when "01100"=>out_h<="0001";out_l<="0010";
		when "01101"=>out_h<="0001";out_l<="0011";
		when "01110"=>out_h<="0001";out_l<="0100";
		when "01111"=>out_h<="0001";out_l<="0101";
		when "10000"=>out_h<="0001";out_l<="0110";
		when "10001"=>out_h<="0001";out_l<="0111";
		when "10010"=>out_h<="0001";out_l<="1000";
		when "10011"=>out_h<="0001";out_l<="1001";
		when "10100"=>out_h<="0010";out_l<="0000";
		when "10101"=>out_h<="0010";out_l<="0001";
		when "10110"=>out_h<="0010";out_l<="0010";
		when "10111"=>out_h<="0010";out_l<="0011";
		when "11000"=>out_h<="0010";out_l<="0100";
		when "11001"=>out_h<="0010";out_l<="0101";
		when "11010"=>out_h<="0010";out_l<="0110";
		when "11011"=>out_h<="0010";out_l<="0111";
		when "11100"=>out_h<="0010";out_l<="1000";
		when "11101"=>out_h<="0010";out_l<="1001";
		when "11110"=>out_h<="0010";out_l<="0000";
		when "11111"=>out_h<="0011";out_l<="0001";
		when others=>out_h<="0000";out_l<="0000";
	end case;
	end process;
end;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity machine is
	port(clk,mode,rst,car: in std_logic;
		count_out1,count_out2: out std_logic_vector(4 downto 0);
        red1,green1,yellow1,red2,green2,yellow2: out std_logic);
end machine;

architecture machine_arc of machine is
	type state is (s1,s2,s3,s4);
	signal present_state: state:=s1;
	signal zt: integer range 3 downto 0;
begin
	process(clk,mode,rst)
		variable count1: std_logic_vector(4 downto 0):="01111";
		variable count2: std_logic_vector(4 downto 0):="01010";
	begin
	if rst='0' then 
		present_state<=s1;count1:="01111";count2:="01010";zt<=0;
	elsif clk'event and clk='1' then
		if mode='0' then
			count1:="01111";count2:="01010";
			present_state<=s1;zt<=0;
		else
			count1:=count1-1;
			count2:=count2-1;                                                   
			if count1="00101" and zt=0 then
        		present_state<=s2; count2:="00101"; zt<=zt+1;
        	elsif count1="00000" and zt=1 then 
        		present_state<=s3; count1:="11001"; count2:="11110"; zt<=zt+1;
        	elsif count2="00101" and zt=2 then 
        		present_state<=s4; count1:="00101"; zt<=zt+1;
        	elsif count2="00000" and zt=3 then 
        		present_state<=s1; count1:="01111"; count2:="01010"; zt<=0;
        	end if;
		end if;
	end if;
	count_out1<=count1;
	count_out2<=count2;
	end process;
 
	process(present_state,mode,car)
	begin
	if mode='0' then
		if car='0' then
			red1<='0'; green1<='1'; yellow1<='1'; red2<='1'; green2<='0'; yellow2<='1';
		else
			red1<='1'; green1<='0'; yellow1<='1'; red2<='0'; green2<='1'; yellow2<='1';
		end if;
	else
		case present_state is
	        when s1=>red1<='0'; green1<='1'; yellow1<='1'; red2<='1'; green2<='0'; yellow2<='1';
	        when s2=>red1<='0'; green1<='1'; yellow1<='1'; red2<='1'; green2<='1'; yellow2<='0';
	        when s3=>red1<='1'; green1<='0'; yellow1<='1'; red2<='0'; green2<='1'; yellow2<='1';
	        when s4=>red1<='1'; green1<='1'; yellow1<='0'; red2<='0'; green2<='1'; yellow2<='1';
	        end case;
	end if;
	end process;
end;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SCAN_LED is
port(CLK:in std_logic;
		M_H:in std_logic_vector(3 downto 0);
		M_L:in std_logic_vector(3 downto 0);
		S_H:in std_logic_vector(3 downto 0);
		S_L:in std_logic_vector(3 downto 0);
		sg:out std_logic_vector(6 downto 0);
		bt:out std_logic_vector(7 downto 0));
end;
architecture one of SCAN_LED is
signal cnt8:std_logic_vector(2 downto 0);
signal a:std_logic_vector(3 downto 0);
begin
p1:process(cnt8)
   begin
   case cnt8 is
	when "000"=>bt<="11111110";a<=S_L;
	when "001"=>bt<="11111101";a<=S_H;
	when "010"=>bt<="11111011";a<="0000";
	when "011"=>bt<="11110111";a<="0000";
	when "100"=>bt<="11101111";a<="0000";
	when "101"=>bt<="11011111";a<="0000";
	when "110"=>bt<="10111111";a<=M_L;
	when "111"=>bt<="01111111";a<=M_H;
	when others=>null;
	end case;
end process p1;
p2:process(CLK)
	begin
	if CLK'event and CLK='1' then
	cnt8<=cnt8+1;
	end if;
end process p2;
p3:process(a)
	begin
	case a is
	when "0000"=>sg<="1000000";
	when "0001"=>sg<="1111001";
	when "0010"=>sg<="0100100";
	when "0011"=>sg<="0110000";
	when "0100"=>sg<="0011001";
	when "0101"=>sg<="0010010";
	when "0110"=>sg<="0000010";
	when "0111"=>sg<="1111000";
	when "1000"=>sg<="0000000";
	when "1001"=>sg<="0010000";
	when "1010"=>sg<="0001000";
	when "1011"=>sg<="0000011";
	when "1100"=>sg<="1000110";
	when "1101"=>sg<="0100001";
	when "1110"=>sg<="0000110";
	when "1111"=>sg<="0001110";
	when others=>null;
	end case;
end process p3;
end;

library	ieee;
use	ieee.std_logic_1164.all;
use	ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_bit.all;

entity int_div	is
generic
	(
	f_div:integer:=48000000;
	f_div_width:integer:=32
	);
port(
	clock    :	in	std_logic;
	clock_out:	out	std_logic
	);
end;

architecture one of	int_div	is
signal clk_p_r:	std_logic;
signal clk_n_r:	std_logic;
signal count_p:	std_logic_vector(f_div_width-1	downto 0);
signal count_n:	std_logic_vector(f_div_width-1	downto 0);
signal clock_out_r:std_logic;

signal full_div_p:	std_logic;
signal half_div_p:	std_logic;
signal full_div_n:	std_logic;
signal half_div_n:	std_logic;

begin
clock_out<=clock_out_r;
full_div_p<='1' when (count_p<f_div-1) 		else '0';
half_div_p<='1' when (count_p<(f_div/2 )-1) else '0';
full_div_n<='1' when (count_n<f_div -1) 	else '0';
half_div_n<='1' when (count_n<(f_div/2)-1)	else '0';

process(clock)
begin
	if	rising_edge(clock)then
		if full_div_p='1' then
			count_p<=count_p+1;
			if (half_div_p='1') then
				clk_p_r<='0';
			else
				clk_p_r<='1';
			end if;
		else
			count_p<= (others =>'0');
			clk_p_r<= '0';
		end if;
	end if;
end process;

process(clock)
begin
	if	falling_edge(clock)then
		if  full_div_n='1'  then
			count_n<=count_n+1;
			if half_div_n='1' then
				clk_n_r<='0';
			else
				clk_n_r<='1';				
			end if;
		else
			count_n<=(others =>'0');
			clk_n_r <= '0';
		end if;
	end if;
end process;

process(clock)
begin
	if	rising_edge(clock)then
		if f_div= 1 then
			clock_out_r<=clock;
		else
			if (f_div rem 2) =1 then
				clock_out_r<= clk_p_r and clk_n_r;
			else
				clock_out_r<=clk_p_r;
			end if;				
		end if;
	end if;
end process;
end;