Quartus II 实现全加器

期末裸考系列之例化语句实现全加器

全加器有两个半加器以及一个或门实现

1.半加器 （h_adder）

library ieee;
use ieee.std_logic_1164.all;
ENTITY h_adder is
	port(A , B : in  std_logic;
	     CO,SO : out std_logic);
END ENTITY h_adder;
ARCHITECTURE two of h_adder is
 begin 
 CO <= A and B;
 SO <= A xor B;
 end ARCHITECTURE two;

2.或门 (or2a)

library ieee;
use ieee.std_logic_1164.all;
ENTITY or2a is
	port(a,b : in  std_logic;
	       c : out std_logic);
END ENTITY or2a;
ARCHITECTURE one of or2a is
 begin 
 c<=a or b;
 end ARCHITECTURE one;

3.全加器实现(f_adder)

library ieee;
use ieee.std_logic_1164.all;
ENTITY f_adder is
	port(ain,bin,cin : in  std_logic;
	     CONT,SUM : out std_logic);
END ENTITY f_adder;
ARCHITECTURE three of f_adder is
	component h_adder is
			port(A , B : in  std_logic;
	           CO,SO : out std_logic);
END component;
	component or2a is
		port(a,b : in  std_logic;
	          c : out std_logic);
END component;
signal net1,net2,net3 : std_logic;
	begin 
		u1 : h_adder port map (A => ain, B => bin, CO => net2, SO => net1);
		u2 : h_adder port map (A => net1, B => cin, CO => net3, SO => SUM);
		u3 : or2a    port map (a => net2,b=>net3,c=>CONT);
		
		
 end ARCHITECTURE three;