期末裸考系列之 例化语句实现计数器
全加器用一个十进制计数器以及一个六进制计数器实现
1.十进制(count10)
library ieee;
use ieee.std_logic_1164.all;
entity count10 is
port(clock,enable:in std_logic;
q:out integer range 0 to 9;
tc:out std_logic);
end count10;
architecture one of count10 is
begin
process (clock )
variable count :integer range 0 to 9;
begin
if clock'event and clock='1' then
if enable='1' then
if count<9 then count :=count+1;
else count:=0;
end if;
end if;
end if;
if(count=9) and ( enable='1')then tc<='1';
else tc<='0';
end if;
q<=count;
end process;
end one;
2.六进制
library ieee;
use ieee.std_logic_1164.all;
entity count6 is
port(clock,enable:in std_logic;
q:out integer range 0 to 5;
tc:out std_logic);
end count6;
architecture two of count6 is
begin
process (clock )
variable count :integer range 0 to 5;
begin
if clock'event and clock='1' then
if enable='1' then
if count<5 then count :=count+1;
else count:=0;
end if;
end if;
end if;
if(count=5) and (enable='1')
then tc<='1';
else tc<='0';
end if;
q<=count;
end process;
end two;
3.实现60进制
library ieee;
use ieee.std_logic_1164.all;
entity count60 is
port(clk,ena : in std_logic;
tens: out integer range 0 to 5;
ones: out integer range 0 to 9;
tc : out std_logic);
end count60;
architecture three of count60 is
signal cascade_wire : std_logic;
component count6
port(clock,enable:in std_logic;
q:out integer range 0 to 5;
tc:out std_logic);
end component;
component count10
port(clock,enable:in std_logic;
q:out integer range 0 to 9;
tc:out std_logic);
end component;
begin
mod10:count10 port map(clock=>clk,enable=>ena, q=>ones,tc=>cascade_wire);
mod6: count6 port map(clock=>clk,enable=>cascade_wire,q=>tens, tc=>tc);
end;