Quartus II 实现7段数码显示译码器

期末裸考系列之 7段数码显示译码器

library ieee;
use ieee.std_logic_1164.all;
entity shuma is
port (A : in  std_logic_vector(3 downto 0);
		B : out std_logic_vector(6 downto 0));
end entity shuma;
architecture one of shuma is
begin 
process(A)  begin
	case (A) is
		when "0000" => B<="0111111" ;
		when "0001" => B<="0000110" ;
		when "0010" => B<="1011011" ;
		when "0011" => B<="1001111" ;
		when "0100" => B<="1100110" ;
		when "0101" => B<="1101101" ;
		when "0110" => B<="1111101" ;
		when "0111" => B<="0000111" ;
		when "1000" => B<="1111111" ;
		when "1001" => B<="1101111" ;
		when "1010" => B<="1110111" ;
		when "1011" => B<="1111100" ;
		when "1100" => B<="0111001" ;
		when "1101" => B<="1011110" ;
		when "1110" => B<="1111011" ;
		when "1111" => B<="1110001" ;
		when others => NULL;
		end case;
	end process;
end one;