Quartus II 实现实用计数器设计（74LS160计数器）

期末裸考系列之实用计数器设计（74LS160计数器）

案例为计数10

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
	port (clk, rst, en, load : std_logic;
	data : in std_logic_vector(3 downto 0);
	dout : out std_logic_vector(3 downto 0);
	cont : out std_logic);
end entity;

architecture one of cnt10 is 
begin 
	process(clk, rst, en, load)
		variable q : std_logic_vector(3 downto 0);
	begin 
		if rst = '0' then Q := (others => '0');
		elsif clk'event and clk = '1' then 
			if en = '1' then 
				if (load = '0') then q := data; else 
					if q<9 then q := q+1;
						else q :=(others => '0');
					end if;
				end if;
			end if;
		end if;
	if q = "1001" then cont <= '1';
		else cont <= '0';
	end if;
	dout <= q;
	end process;
end one;