Lattice DCS (Dynamic Clock Select)

Lattice DCS (Dynamic Clock Select)
1、Why do I get a netsanitycheck PAR error when a MUX drives the clock of a IDDR/ODDR component?
The netsanitycheck error indicates general routing is used to drive the IDDR and/or ODDR components. The logic must be modified to use dedicated clock resources:Solution 1: Do not use generic logic (e.g. MUX implemented by LUTs) to generate the clock for the IDDR/ODDR. The solution is to use a DCS for the MUX function instead. Solution 2: Use the dedicated clock routing resources when using a DCS. A typical application is to use the DCS to switch between a PLL input and PLL output clock. But beware, if a dedicated PLL input pin and the PLL CLKOS output are the two inputs of a DCS, the PLL input pin will go to the DCS via the general routing net. There are two possible work-arounds: A) Route the PLL input to the PLL’s CLKOK while bypassing the PLL. Then the CLKOS and the CLKOK PLL outputs can be connected to the DCS with the dedicated routing resource. b) Route the PLL input from a primary clock pin, not a PLL input pin. The PLL input and the CLKOS can be fed to the DCS directly without any problem.
2、How to locate DCS in preference file for FPGA?
DCS is a Digital clock select, a clock multiplexer, which is available in devices such as LatticeSC/M, LatticeXP2, LatticeECP2/M and LatticeECP3.
How to assign DCS locations in .lpf preference file?The syntax is shown in the following example: LOCATE COMP “xxxx” SITE “DCSTB” ; The “xxxx” is the instantiation name in your VHDL or Verilog code.
The DCS locations in LatticeSC family are at four edges – two per edge.DCSTA, DCSTBDCSLA, DCSLBDCSRA, DCSRBDCSBA, DCSBBwhere the letter right after “DCS” shows the edge the DCS is located: T is top, L is left, R is right, B is bottom.
The DCS locations in LatticeXP2, LatticeECP2/M and LatticeECP3 families are near the Center S