GD32 串口重映射问题

于 2023-04-18 21:49:22 发布
阅读量2.3k 收藏 15
点赞数 4
文章标签： 单片机 stm32 驱动开发
版权声明：本文为博主原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接和本声明。
本文链接：https://blog.csdn.net/world9999/article/details/130231182
版权

标题GD32 串口重映射问题

一、重映射端口描述

以下是GD32F205的USART remap说明
在这里插入图片描述
在这里插入图片描述
在这里插入图片描述

二、代码实现

使用重映射功能必须开启AF时钟，如下

rcu_periph_clock_enable(RCU_AF);

以下是USART1 remap代码

gpio_pin_remap_config(GPIO_USART1_REMAP, ENABLE);

三、注意事项

只有USART0、USART1、USART2重映射调用函数gpio_pin_remap_config，其余串口要调用函数gpio_pin_remap1_config，二者的区别和使用方法参考库文件的注释说明。

/*!
    \brief      configure GPIO pin remap
    \param[in]  gpio_remap: select the pin to remap
      \arg        GPIO_SPI0_REMAP: SPI0 remapping
      \arg        GPIO_I2C0_REMAP: I2C0 remapping
      \arg        GPIO_USART0_REMAP: USART0 remapping
      \arg        GPIO_USART1_REMAP: USART1 remapping
      \arg        GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping
      \arg        GPIO_USART2_FULL_REMAP: USART2 full remapping
      \arg        GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping 
      \arg        GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping
      \arg        GPIO_TIMER1_PARTIAL_REMAP0: TIMER1 partial remapping
      \arg        GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping
      \arg        GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping
      \arg        GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping
      \arg        GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping
      \arg        GPIO_TIMER3_REMAP: TIMER3 remapping
      \arg        GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping
      \arg        GPIO_CAN0_FULL_REMAP: CAN0 full remapping
      \arg        GPIO_PD01_REMAP: PD01 remapping
      \arg        GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping
      \arg        GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping
      \arg        GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping
      \arg        GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping
      \arg        GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping
      \arg        GPIO_ENET_REMAP: ENET remapping
      \arg        GPIO_CAN1_REMAP: CAN1 remapping
      \arg        GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST
      \arg        GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled
      \arg        GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled
      \arg        GPIO_SPI2_REMAP: SPI2 remapping
      \arg        GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping
      \arg        GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping 
      \arg        GPIO_TIMER8_REMAP: TIMER8 remapping
      \arg        GPIO_TIMER9_REMAP: TIMER9 remapping
      \arg        GPIO_TIMER10_REMAP: TIMER10 remapping
      \arg        GPIO_TIMER12_REMAP: TIMER12 remapping
      \arg        GPIO_TIMER13_REMAP: TIMER13 remapping
      \arg        GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect
    \param[in]  newvalue: ENABLE or DISABLE
    \param[out] none
    \retval     none
*/
void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue)
{
    uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U;

    if(AFIO_PCF1_FIELDS == (gpio_remap & AFIO_PCF1_FIELDS)){
        /* get AFIO_PCF1 regiter value */
        temp_reg = AFIO_PCF1;
    }else{
        /* get AFIO_PCF0 regiter value */
        temp_reg = AFIO_PCF0;
    }

    temp_mask = (gpio_remap & PCF_POSITION_MASK) >> 0x10U;
    remap1 = gpio_remap & LSB_16BIT_MASK;

    /* judge pin remap type */
    if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (gpio_remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){
        temp_reg &= PCF_SWJCFG_MASK;
        AFIO_PCF0 &= PCF_SWJCFG_MASK;
    }else if(PCF_LOCATION2_MASK == (gpio_remap & PCF_LOCATION2_MASK)){
        remap2 = ((uint32_t)0x03U) << temp_mask;
        temp_reg &= ~remap2;
        temp_reg |= ~PCF_SWJCFG_MASK;
    }else{
        temp_reg &= ~(remap1 << ((gpio_remap >> 0x15U)*0x10U));
        temp_reg |= ~PCF_SWJCFG_MASK;
    }
    
    /* set pin remap value */
    if(DISABLE != newvalue){
        temp_reg |= (remap1 << ((gpio_remap >> 0x15U)*0x10U));
    }
    
    if(AFIO_PCF1_FIELDS == (gpio_remap & AFIO_PCF1_FIELDS)){
        /* set AFIO_PCF1 regiter value */
        AFIO_PCF1 = temp_reg;
    }else{
        /* set AFIO_PCF0 regiter value */
        AFIO_PCF0 = temp_reg;
    }
}

/*!
    \brief      configure GPIO pin remap1
    \param[in]  remap_reg: 
      \arg        GPIO_PCF2: AFIO port configuration register 2
      \arg        GPIO_PCF3: AFIO port configuration register 3
      \arg        GPIO_PCF4: AFIO port configuration register 4
      \arg        GPIO_PCF5: AFIO port configuration register 5
    \param[in]  remap: select the pin to remap
      \arg        GPIO_PCF2_DCI_VSYNC_PG9_REMAP: DCI VSYNC remapped to PG9
      \arg        GPIO_PCF2_DCI_VSYNC_PI5_REMAP: DCI VSYNC remapped to PI5
      \arg        GPIO_PCF2_DCI_D0_PC6_REMAP: DCI D0 remapped to PC6
      \arg        GPIO_PCF2_DCI_D0_PH9_REMAP: DCI D0 remapped to PH9
      \arg        GPIO_PCF2_DCI_D1_PC7_REMAP: DCI D1 remapped to PC7
      \arg        GPIO_PCF2_DCI_D1_PH10_REMAP: DCI D1 remapped to PH10
      \arg        GPIO_PCF2_DCI_D2_PE0_REMAP: DCI D2 remapped to PE0
      \arg        GPIO_PCF2_DCI_D2_PG10_REMAP: DCI D2 remapped to PG10
      \arg        GPIO_PCF2_DCI_D2_PH11_REMAP: DCI D2 remapped to PH11
      \arg        GPIO_PCF2_DCI_D3_PE1_REMAP: DCI D3 remapped to PE1
      \arg        GPIO_PCF2_DCI_D3_PG11_REMAP: DCI D3 remapped to PG11
      \arg        GPIO_PCF2_DCI_D3_PH12_REMAP: DCI D3 remapped to PH12
      \arg        GPIO_PCF2_DCI_D4_PE4_REMAP: DCI D4 remapped to PE4
      \arg        GPIO_PCF2_DCI_D4_PH14_REMAP: DCI D4 remapped to PH14
      \arg        GPIO_PCF2_DCI_D5_PD3_REMAP: DCI D5 remapped to PD3
      \arg        GPIO_PCF2_DCI_D5_PI4_REMAP: DCI D5 remapped to PI4
      \arg        GPIO_PCF2_DCI_D6_PE5_REMAP: DCI D6 remapped to PE5
      \arg        GPIO_PCF2_DCI_D6_PI6_REMAP: DCI D6 remapped to PI6 
      \arg        GPIO_PCF2_DCI_D7_PE6_REMAP: DCI D7 remapped to PE6 
      \arg        GPIO_PCF2_DCI_D7_PI7_REMAP: DCI D7 remapped to PI7 
      \arg        GPIO_PCF2_DCI_D8_PH6_REMAP: DCI D8 remapped to PH6 
      \arg        GPIO_PCF2_DCI_D8_PI1_REMAP: DCI D8 remapped to PI1 
      \arg        GPIO_PCF2_DCI_D9_PH7_REMAP: DCI D9 remapped to PH7 
      \arg        GPIO_PCF2_DCI_D9_PI2_REMAP: DCI D9 remapped to PI2 
      \arg        GPIO_PCF2_DCI_D10_PD6_REMAP: DCI D10 remapped to PD6 
      \arg        GPIO_PCF2_DCI_D10_PI3_REMAP: DCI D10 remapped to PI3 
      \arg        GPIO_PCF2_DCI_D11_PF10_REMAP: DCI D11 remapped to PF10 
      \arg        GPIO_PCF2_DCI_D11_PH15_REMAP: DCI D11 remapped to PH15 
      \arg        GPIO_PCF2_DCI_D12_PG6_REMAP: DCI D12 remapped to PG6 
      \arg        GPIO_PCF2_DCI_D13_PG15_REMAP: DCI D12 remapped to PG15 
      \arg        GPIO_PCF2_DCI_D13_PI0_REMAP: DCI D13 remapped to PI0 
      \arg        GPIO_PCF2_DCI_HSYNC_PH8_REMAP: DCI HSYNC to PH8 
      \arg        GPIO_PCF2_PH01_REMAP: PH0/PH1 remapping 
      \arg        GPIO_PCF3_TLI_B5_PA3_REMAP: TLI B5 remapped to PA3 
      \arg        GPIO_PCF3_TLI_VSYNC_PA4_REMAP: TLI VSYNC remapped to PA4 
      \arg        GPIO_PCF3_TLI_G2_PA6_REMAP: TLI G2 remapped to PA6 
      \arg        GPIO_PCF3_TLI_R6_PA8_REMAP: TLI R6 remapped to PA8 
      \arg        GPIO_PCF3_TLI_R4_PA11_REMAP: TLI R4 remapped to PA11 
      \arg        GPIO_PCF3_TLI_R5_PA12_REMAP: TLI R5 remapped to PA12 
      \arg        GPIO_PCF3_TLI_R3_PB0_REMAP: TLI R3 remapped to PB0 
      \arg        GPIO_PCF3_TLI_R6_PB1_REMAP: TLI R6 remapped to PB1 
      \arg        GPIO_PCF3_TLI_B6_PB8_REMAP: TLI B6 remapped to PB8 
      \arg        GPIO_PCF3_TLI_B7_PB9_REMAP: TLI B7 remapped to PB9 
      \arg        GPIO_PCF3_TLI_G4_PB10_REMAP: TLI G4 remapped to PB10 
      \arg        GPIO_PCF3_TLI_G5_PB11_REMAP: TLI G5 remapped to PB11 
      \arg        GPIO_PCF3_TLI_HSYNC_PC6_REMAP: TLI HSYNC remapped to PC6 
      \arg        GPIO_PCF3_TLI_G6_PC7_REMAP: TLI G6 remapped to PC7 
      \arg        GPIO_PCF3_TLI_R2_PC10_REMAP: TLI R2 remapped to PC10 
      \arg        GPIO_PCF3_TLI_G7_PD3_REMAP: TLI G7 remapped to PD3 
      \arg        GPIO_PCF3_TLI_B2_PD6_REMAP: TLI B2 remapped to PD6 
      \arg        GPIO_PCF3_TLI_B3_PD10_REMAP: TLI B3 remapped to PD10 
      \arg        GPIO_PCF3_TLI_B0_PE4_REMAP: TLI B0 remapped to PE4 
      \arg        GPIO_PCF3_TLI_G0_PE5_REMAP: TLI G0 remapped to PE5 
      \arg        GPIO_PCF3_TLI_G1_PE6_REMAP: TLI G1 remapped to PE6 
      \arg        GPIO_PCF3_TLI_G3_PE11_REMAP: TLI G3 remapped to PE11 
      \arg        GPIO_PCF3_TLI_B4_PE12_REMAP: TLI B4 remapped to PE12 
      \arg        GPIO_PCF3_TLI_DE_PE13_REMAP: TLI DE remapped to PE13 
      \arg        GPIO_PCF3_TLI_CLK_PE14_REMAP: TLI CLK remapped to PE14 
      \arg        GPIO_PCF3_TLI_R7_PE15_REMAP: TLI R7 remapped to PE15 
      \arg        GPIO_PCF3_TLI_DE_PF10_REMAP: TLI DE remapped to PF10 
      \arg        GPIO_PCF3_TLI_R7_PG6_REMAP: TLI R7 remapped to PG6 
      \arg        GPIO_PCF3_TLI_CLK_PG7_REMAP: TLI CLK remapped to PG7 
      \arg        GPIO_PCF3_TLI_G3_PG10_REMAP: TLI G3 remapped to PG10 
      \arg        GPIO_PCF3_TLI_B2_PG10_REMAP: TLI B2 remapped to PG10 
      \arg        GPIO_PCF3_TLI_B3_PG11_REMAP: TLI B3 remapped to PG11 
      \arg        GPIO_PCF4_TLI_B4_PG12_REMAP: B4 remapped to PG12 
      \arg        GPIO_PCF4_TLI_B1_PG12_REMAP: B1 remapped to PG12 
      \arg        GPIO_PCF4_TLI_R0_PH2_REMAP2: R0 remapped to PH2 
      \arg        GPIO_PCF4_TLI_R1_PH3_REMAP: TLI R1 remapped to PH3 
      \arg        GPIO_PCF4_TLI_R2_PH8_REMAP: TLI R2 remapped to PH8 
      \arg        GPIO_PCF4_TLI_R3_PH9_REMAP: TLI R3 remapped to PH9 
      \arg        GPIO_PCF4_TLI_R4_PH10_REMAP: TLI R4 remapped to PH10 
      \arg        GPIO_PCF4_TLI_R5_PH11_REMAP: TLI R5 remapped to PH11 
      \arg        GPIO_PCF4_TLI_R6_PH12_REMAP: TLI R6 remapped to PH12 
      \arg        GPIO_PCF4_TLI_G2_PH13_REMAP: TLI G2 remapped to PH13 
      \arg        GPIO_PCF4_TLI_G3_PH14_REMAP: TLI G3 remapped to PH14 
      \arg        GPIO_PCF4_TLI_G4_PH15_REMAP: TLI G4 remapped to PH15 
      \arg        GPIO_PCF4_TLI_G5_PI0_REMAP: TLI G5 remapped to PI0 
      \arg        GPIO_PCF4_TLI_G6_PI1_REMAP: TLI G6 remapped to PI1 
      \arg        GPIO_PCF4_TLI_G7_PI2_REMAP: TLI G7 remapped to PI2 
      \arg        GPIO_PCF4_TLI_B4_PI4_REMAP: TLI B4 remapped to PI4 
      \arg        GPIO_PCF4_TLI_B5_PI5_REMAP: TLI B5 remapped to PI5 
      \arg        GPIO_PCF4_TLI_B6_PI6_REMAP: TLI B6 remapped to PI6 
      \arg        GPIO_PCF4_TLI_B7_PI7_REMAP: TLI B7 remapped to PI7 
      \arg        GPIO_PCF4_TLI_VSYNC_PI9_REMAP: TLI VSYNC remapped to PI9 
      \arg        GPIO_PCF4_TLI_HSYNC_PI10_REMAP: TLI HSYNC remapped to PI10 
      \arg        GPIO_PCF4_TLI_R0_PH4_REMAP: TLI R0 remapped to PH4 
      \arg        GPIO_PCF4_TLI_R1_PI3_REMAP: TLI R1 remapped to PI3 
      \arg        GPIO_PCF4_SPI1_SCK_PD3_REMAP: SPI1 SCK remapped to PD3 
      \arg        GPIO_PCF4_SPI2_MOSI_PD6_REMAP: SPI2 MOSI remapped to PD6 
      \arg        GPIO_PCF5_I2C2_REMAP0: I2C2 remapping 0 
      \arg        GPIO_PCF5_I2C2_REMAP1: I2C2 remapping 1 
      \arg        GPIO_PCF5_TIMER1_CH0_REMAP: TIMER1 CH0 remapped to PA5 
      \arg        GPIO_PCF5_TIMER4_REMAP: TIMER4 CH0 remapping 
      \arg        GPIO_PCF5_TIMER7_CHON_REMAP0: TIMER7 CHON remapping 0 
      \arg        GPIO_PCF5_TIMER7_CHON_REMAP1: TIMER7 CHON remapping 1 
      \arg        GPIO_PCF5_TIMER7_CH_REMAP: TIMER7 CH remapping 
      \arg        GPIO_PCF5_I2C1_REMAP0: I2C1 remapping 0 
      \arg        GPIO_PCF5_I2C1_REMAP1: I2C1 remapping 1 
      \arg        GPIO_PCF5_SPI1_NSCK_REMAP0: SPI1 NSS/SCK remapping 0 
      \arg        GPIO_PCF5_SPI1_NSCK_REMAP1: SPI1 NSS/SCK remapping 1 
      \arg        GPIO_PCF5_SPI1_IO_REMAP0: SPI1 MISO/MOSI remapping 0 
      \arg        GPIO_PCF5_SPI1_IO_REMAP1: SPI1 MISO/MOSI remapping 1 
      \arg        GPIO_PCF5_UART3_REMAP: UART3 remapping 
      \arg        GPIO_PCF5_TIMER11_REMAP: TIMER11 remapping 
      \arg        GPIO_PCF5_CAN0_ADD_REMAP: CAN0 addition remapping 
      \arg        GPIO_PCF5_ENET_TXD3_REMAP: ETH_TXD3 remapped to PE2 
      \arg        GPIO_PCF5_PPS_HI_REMAP: ETH_PPS_OUT remapped to PG8 
      \arg        GPIO_PCF5_ENET_TXD01_REMAP: ETH_TX_EN/ETH_TXD0/ETH_TXD1 remapping 
      \arg        GPIO_PCF5_ENET_CRSCOL_REMAP: ETH_MII_CRS/ETH_MII_COL remapping 
      \arg        GPIO_PCF5_ENET_RX_HI_REMAP: ETH_RXD2/ETH_RXD3/ETH_RX_ER remapping 
      \arg        GPIO_PCF5_UART6_REMAP: UART6 remapping 
      \arg        GPIO_PCF5_USART5_CK_PG7_REMAP: USART5 CK remapped to PG7 
      \arg        GPIO_PCF5_USART5_RTS_PG12_REMAP: USART5 RTS remapped to PG12 
      \arg        GPIO_PCF5_USART5_CTS_PG13_REMAP: USART5 CTS remapped to PG13 
      \arg        GPIO_PCF5_USART5_TX_PG14_REMAP: USART5 TX remapped to PG14 
      \arg        GPIO_PCF5_USART5_RX_PG9_REMAP: USART5 RX remapped to PG9 
      \arg        GPIO_PCF5_EXMC_SDNWE_PC0_REMAP: EXMC SDNWE remapped to PC0 
      \arg        GPIO_PCF5_EXMC_SDCKE0_PC3_REMAP: EXMC SDCKE0 remapped to PC3 
      \arg        GPIO_PCF5_EXMC_SDCKE1_PB5_REMAP: EXMC SDCKE1 remapped to PB5 
      \arg        GPIO_PCF5_EXMC_SDNE0_PC2_REMAP: EXMC SDNE0 remapped to PC2
      \arg        GPIO_PCF5_EXMC_SDNE1_PB6_REMAP: EXMC SDNE1 remapped to PB6
    \param[in]  newvalue: ENABLE or DISABLE
    \param[out] none
    \retval     none
*/
void gpio_pin_remap1_config(uint8_t remap_reg, uint32_t remap, ControlStatus newvalue)
{
    uint32_t reg = 0U;

    if(DISABLE != newvalue){
        /* AFIO port configuration register selection */
        if(GPIO_PCF2 == remap_reg){
            reg = AFIO_PCF2;
            reg |= remap;
            AFIO_PCF2 = reg;
        }else if(GPIO_PCF3 == remap_reg){
            reg = AFIO_PCF3;
            reg |= remap;
            AFIO_PCF3 = reg;
        }else if(GPIO_PCF4 == remap_reg){
            reg = AFIO_PCF4;
            reg |= remap;
            AFIO_PCF4 = reg;
        }else if(GPIO_PCF5 == remap_reg){
            reg = AFIO_PCF5;
            reg |= remap;
            AFIO_PCF5 = reg;
        }else{
            /* illegal parameters */
        }
    }else{
        if(GPIO_PCF2 == remap_reg){
            reg = AFIO_PCF2;
            reg &= ~remap;
            AFIO_PCF2 = reg;
        }else if(GPIO_PCF3 == remap_reg){
            reg = AFIO_PCF3;
            reg &= ~remap;
            AFIO_PCF3 = reg;
        }else if(GPIO_PCF4 == remap_reg){
            reg = AFIO_PCF4;
            reg &= ~remap;
            AFIO_PCF4 = reg;
        }else if(GPIO_PCF5 == remap_reg){
            reg = AFIO_PCF5;
            reg &= ~remap;
            AFIO_PCF5 = reg;
        }else{
            /* illegal parameters */
        }
    }
}

注意二者的区别和作用范围：
void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue)
void gpio_pin_remap1_config(uint8_t remap_reg, uint32_t remap, ControlStatus newvalue)
后者比前者多了一个参数remap_reg，其值为GPIO_PCF2、GPIO_PCF3、GPIO_PCF4或者GPIO_PCF5。其实gpio_pin_remap_config默认操作的是GPIO_PCF0和GPIO_PCF1，因此二者本质上是一样的。调用时一定要选用正确的函数，曾经笔者在重映射UART3时，参考USART1的方法，直接调用了gpio_pin_remap_config函数，编译并不会报错，但UART3不能正常工作，因此在这里花费了很长时间寻找问题。下面将USART1个UART3重映射的正确调用方法列出供对比参考。

gpio_pin_remap_config(GPIO_USART1_REMAP, ENABLE);  //USART1重映射
gpio_pin_remap1_config(GPIO_PCF5, GPIO_PCF5_UART3_REMAP, ENABLE);  //UART3重映射

三、举一反三

本文用串口作为例子讲解如何进行端口重映射，其他外设操作方法类似。比如采用PB3和PB4作为正常IO时就需要重映射，因为这两个IO默认用作JTAG。
在这里插入图片描述
调用以下代码重映射之后就可以正常使用PB3和PB4了。

gpio_pin_remap_config(GPIO_SWJ_NONJTRST_REMAP, ENABLE);
gpio_pin_remap_config(GPIO_SWJ_SWDPENABLE_REMAP, ENABLE);

四、总结

多看手册，多看代码，多看注释，还得多思考！

world9999
关注
  • 4
    点赞
  • 踩
  • 15
    收藏
    觉得还不错? 一键收藏
  • 1
    评论
评论 1
添加红包

请填写红包祝福语或标题

个

红包个数最小为10个

元

红包金额最低5元

当前余额3.43元 前往充值 >
需支付：10.00元
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付元
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明：

1.余额是钱包充值的虚拟货币，按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载，可以购买VIP、付费专栏及课程。

余额充值