if options.l3cache:
if options.cpu_type == "arm_detailed":
system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc,
block_size=options.cacheline_size)
else:
system.l3 = L3Cache(size = options.l3_size, assoc = options.l3_assoc,
block_size=options.cacheline_size)
system.tol3bus = CoherentBus()
system.l3.cpu_side = system.tol3bus.master
system.l3.mem_side = system.membus.slave
for i in xrange(options.num_cpus):
system.cpu[i].l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
block_size=options.cacheline_size)
system.cpu[i].tol2bus = CoherentBus()
system.cpu[i].l2.cpu_side = system.cpu[i].tol2b