History of Verilog HDL

History Of Verilog

Verilog was started initially as a proprietary hardware modeling language by Gateway Design Automation Inc. around 1984. It is rumored that the original language was designed by taking features from the most popular HDL language of the time, called HiLo, as well as from traditional computer languages such as C. At that time, Verilog was not standardized and the language modified itself in almost all the revisions that came out within 1984 to 1990.

1984年，Verilog HDL 最初源于 Gateway Design Automation（网关的自动化设计）公司的所有的硬件建模语言。

据说，原始的语言从在硬件描述语言时代非常流行的称之为HiLo的HDL语言和传统的计算机编程语言如C语言中吸收了他们的特征。当时，Verilog HDL还没有被标准化, 并且在1984年到1990年的所有版本在其所有都修订版中都有所修改。

Verilog simulator was first used beginning in 1985 and was extended substantially through 1987. The implementation was the Verilog simulator sold by Gateway. The first major extension was Verilog-XL, which added a few features and implemented the infamous "XL algorithm" which was a very efficient method for doing gate-level simulation. Verilog HDL 仿真器在1985年第一次使用，在1987年完成其实质 上扩展。这个实现是Gateway公司发售的Verilog 仿真器。第一个主要的扩展是Verilog-XL，其中添加了一些特性 并实现了臭名昭著的XL算法，是一种非常高效的门级仿真算法。

The time was late 1990. Cadence Design System, whose primary product at that time included Thin film process simulator, decided to acquire Gateway Automation System. Along with other Gateway products, Cadence now became the owner of the Verilog language, and continued to market Verilog as both a language and a simulator. At the same time, Synopsys was marketing the top-down design methodology, using Verilog. This was a powerful combination.

到了1990年末，以Thin film process simulator作为主打产品的Cadence Design System公司决定收购Gateway Automation System公司。同时拥有了Gateway公司的其他产品，Cadence成为Verilog 语言的所有者，同时继续出售作为一种语言和仿真器的的verilog。与次同时， Synopsys出售使用verilog的自定向下的设计方法。这是一个强大的组合。

In 1990, Cadence recognized that if Verilog remained a closed language, the pressures of standardization would eventually cause the industry to shift to VHDL. Consequently, Cadence organized the Open Verilog International (OVI), and in 1991 gave it the documentation for the Verilog Hardware Description Language. This was the event which "opened" the language. 在1990年，Cadence公司认为如果Verilog继续作为一种封闭性的语言，标准化的压力将最终将导致业界都转向VHDL。因此，Cadence公司组织了一个开放的verilog国际组织（OVI), 在1991年将其关于Verilog硬件描述语言的的文档交给OVI. 这是一个开放语言的事件。

OVI did a considerable amount of work to improve the Language Reference Manual (LRM), clarifying things and making the language specification as vendor-independent as possible. OVI 为了改进该语言的参考手册（LRM）做出了大量的工作，其中包括，分类和使语言尽可能规范独立于供应商。

Soon it was realized that if there were too many companies in the market for Verilog, potentially everybody would like to do what Gateway had done so far - changing the language for their own benefit. This would defeat the main purpose of releasing the language to public domain. As a result in 1994, the IEEE 1364 working group was formed to turn the OVI LRM into an IEEE standard. This effort was concluded with a successful ballot in 1995, and Verilog became an IEEE standard in December 1995.

不久，意识到市场上有太多的verilog公司为了自身的利益像Gateway公司那样修改语言。将有悖于将Verilog语言公布于大众的初衷。结果，在1994年 IEEE 1364 working group成立，致力于将OVI LRM转化为IEEE标准。在1995年，这方面的努力完成了一个成功的选票，Verilog在1995年12月成一个IEEE的标准。

When Cadence gave OVI the LRM, several companies began working on Verilog simulators. In 1992, the first of these were announced, and by 1993 there were several Verilog simulators available from companies other than Cadence. The most successful of these was VCS, the Verilog Compiled Simulator, from Chronologic Simulation. This was a true compiler as opposed to an interpreter, which is what Verilog-XL was. As a result, compile time was substantial, but simulation execution speed was much faster.

当Cadence 将verilog的LRM交给OVI时，有几家公司开始致力于Verilog仿真器。在1992年，他们中第一批宣布成功，到1993年，

已经有几个可用的非Cadence公司的verilog的仿真器。其中，最成功的是VCS，按时间顺序执行的编译型仿真器。这是一个真正的编译器区别于像Verilog-XL似的解释器。结果，编译花费大量的时间，但是仿真执行的速度变得更快。

In the meantime, the popularity of Verilog and PLI was rising exponentially. Verilog as a HDL found more admirers than well-formed and federally funded VHDL.  It was only a matter of time before people in OVI realized the need of a more universally accepted standard. Accordingly, the board of directors of OVI requested IEEE to form a working committee for establishing Verilog as an IEEE standard. The working committee 1364 was formed in mid 1993 and on October 14, 1993, it had its first meeting. 同时，Verilog和PLI的普及非常迅速。Verlog HDL 比形式规范并且有联邦资助的VHDL有更多的欣赏者。这只是一个时间性的问题，在OVI的人们认识到需要一个更普遍接受的标准之前，OVI董事会董事的要求IEEE成立一个工作委员会建立的Verilog作为IEEE标准。工作委员会1364成立于1993年年中并且1993年10月14日，召开了它的第一次会议。

The standard, which combined both the Verilog language syntax and the PLI in a single volume, was passed in May 1995 and now known as IEEE Std. 1364-1995. 这个将Verilog 语言的语法和PLI组合一起作为一个单卷中的标准，在1995年通过，也就是现在称为IEEE 标准 1364-1995.

After many years, new features have been added to Verilog, and the new version is called Verilog 2001. This version seems to have fixed a lot of problems that Verilog 1995 had. This version is called 1364-2001. 许多年过去了，新的特性被添加到Verilog中，并且新的版本叫Verilog 2001。这个版本好像修正了Verilog1995中问题。 这个version称之为 1364-2001.

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