Verilog HDL Syntax And Semantics Part-III

最新推荐文章于 2023-08-29 19:13:44 发布

wzb56

最新推荐文章于 2023-08-29 19:13:44 发布

阅读量927

点赞数

分类专栏： Verilog

Verilog 专栏收录该内容

39 篇文章 1 订阅

订阅专栏

Hierarchical Identifiers //层次型的标识符

Hierarchical path names are based on the top module identifier followed by module instant identifiers, separated by periods.

层次性的路径名是上层模块的标识符后跟着模块标识符，使用.号来分隔。

This is useful basically when we want to see the signal inside a lower module, or want to force a value inside an internal module. The example below shows how to monitor the value of an internal module signal.

这基本上是非常有用的当我们查看一个底层模块中的一个信号或者为内部模块中设置一个值。下面这个例子，将展示如何监视一个内部模块的信号值。

Example //举例


  1 //-----------------------------------------------------
  2 // This is simple adder Program
  3 // Design Name : adder_hier
  4 // File Name   : adder_hier.v
  5 // Function    : This program shows verilog hier path works
  6 // Coder       : Deepak
  7 //-----------------------------------------------------
  8 `include "addbit.v"
  9 module adder_hier (
 10 result        , // Output of the adder
 11 carry         , // Carry output of adder
 12 r1            , // first input
 13 r2            , // second input
 14 ci              // carry input
 15 );
 16 
 17 // Input Port Declarations       
 18 input    [3:0]   r1         ;
 19 input    [3:0]   r2         ;
 20 input            ci         ;
 21 
 22 // Output Port Declarations
 23 output   [3:0]  result      ;
 24 output          carry       ;
 25 
 26 // Port Wires
 27 wire     [3:0]    r1        ;
 28 wire     [3:0]    r2        ;
 29 wire              ci        ;
 30 wire     [3:0]    result    ;
 31 wire              carry     ;
 32 
 33 // Internal variables
 34 wire              c1        ;
 35 wire              c2        ;
 36 wire              c3        ;
 37 
 38 // Code Starts Here
 39 addbit u0 (r1[0],r2[0],ci,result[0],c1);
 40 addbit u1 (r1[1],r2[1],c1,result[1],c2);
 41 addbit u2 (r1[2],r2[2],c2,result[2],c3);
 42 addbit u3 (r1[3],r2[3],c3,result[3],carry);
 43 
 44 endmodule // End Of Module adder
 45 
 46 module tb();
 47 
 48 reg [3:0] r1,r2;
 49 reg  ci;
 50 wire [3:0] result;
 51 wire  carry;
 52 
 53 // Drive the inputs
 54 initial begin
 55   r1 = 0;
 56   r2 = 0;
 57   ci = 0;
 58    #10  r1 = 10;
 59    #10  r2 = 2;
 60    #10  ci = 1;
 61    #10  $display("+--------------------------------------------------------+");
 62   $finish;
 63 end
 64 
 65 // Connect the lower module
 66 adder_hier U (result,carry,r1,r2,ci);
 67 
 68 // Hier demo here
 69 initial begin
 70   $display("+--------------------------------------------------------+");
 71   $display("|  r1  |  r2  |  ci  | u0.sum | u1.sum | u2.sum | u3.sum |");
 72   $display("+--------------------------------------------------------+");
 73   $monitor("|  %h   |  %h   |  %h   |    %h    |   %h   |   %h    |   %h    |",
 74   r1,r2,ci, tb.U.u0.sum, tb.U.u1.sum, tb.U.u2.sum, tb.U.u3.sum); 
 75 end
 76 
 77 endmodule

You could download file adder_hier.v here

 +--------------------------------------------------------+
 |  r1  |  r2  |  ci  | u0.sum | u1.sum | u2.sum | u3.sum |
 +--------------------------------------------------------+
 |  0   |  0   |  0   |    0    |   0   |   0    |   0    |
 |  a   |  0   |  0   |    0    |   1   |   0    |   1    |
 |  a   |  2   |  0   |    0    |   0   |   1    |   1    |
 |  a   |  2   |  1   |    1    |   0   |   1    |   1    |
 +--------------------------------------------------------+

Data Types //数据类型

Verilog Language has two primary data types: // Verilog HDL 语言有两种基本的数据类型。

Nets - represent structural connections between components. //线网型net表示组件间的链接构件。
Registers - represent variables used to store. //reg， register表示用存储值的变量。

Every signal has a data type associated with it: // 每个信号都有一个数据类型与之关联

Explicitly declared with a declaration in your Verilog code. //显式声明：在你的Verilog HDL代码中显示声明。
Implicitly declared with no declaration when used to connect structural building blocks in your code.
Implicit declaration is always a net type "wire" and is one bit wide.
隐式声明，即没有声明。当用来链接，构建不同的模块时。隐式声明的类型总是一种线网类型，net类型中的wire并且是一位的宽度。

Types of Nets //线网类型 net类型

Each net type has a functionality that is used to model different types of hardware (such as PMOS, NMOS, CMOS, etc)

每一种线网类型具有一种功能，来为不同的硬件类型建模（如PMOS, NMOS，CMOS,等等）。

Net Data Type	Functionality
wire, tri	Interconnecting wire - no special resolution function //连接线，无特殊的决议功能
wor, trior	Wired outputs OR together (models ECL) // or
wand, triand	Wired outputs AND together (models open-collector) // and
tri0, tri1	Net pulls-down or pulls-up when not driven // pull-down , pull -up
supply0, supply1	Net has a constant logic 0 or logic 1 (supply strength) //电源
trireg	Retains last value, when driven by z (tristate). //

Note : Of all net types, wire is the one which is most widely used.

注意：在所有的线网类型中，wire是最常用的类型。

Example - wor //线或


  1 module test_wor();
  2 
  3 wor a;
  4 reg b, c;
  5 
  6 assign a =  b;
  7 assign a =  c;
  8 
  9 initial begin
 10   $monitor("%g a = %b b = %b c = %b", $time, a, b, c);
 11    #1  b  = 0;
 12    #1  c  = 0;
 13    #1  b = 1;
 14    #1  b = 0;
 15    #1  c = 1;
 16    #1  b = 1;
 17    #1  b = 0;
 18    #1  $finish;
 19 end
 20 
 21 endmodule

You could download file test_wor.v here

Simulator Output

 0 a = x b = x c = x
 1 a = x b = 0 c = x
 2 a = 0 b = 0 c = 0
 3 a = 1 b = 1 c = 0
 4 a = 0 b = 0 c = 0
 5 a = 1 b = 0 c = 1
 6 a = 1 b = 1 c = 1
 7 a = 1 b = 0 c = 1

Example - wand //线与


  1 module test_wand();
  2 
  3 wand a;
  4 reg b, c;
  5 
  6 assign a =  b;
  7 assign a =  c;
  8 
  9 initial begin
 10   $monitor("%g a = %b b = %b c = %b", $time, a, b, c);
 11    #1  b  = 0;
 12    #1  c  = 0;
 13    #1  b = 1;
 14    #1  b = 0;
 15    #1  c = 1;
 16    #1  b = 1;
 17    #1  b = 0;
 18    #1  $finish;
 19 end
 20 
 21 endmodule

You could download file test_wand.v here

Simulator Output

 0 a = x b = x c = x
 1 a = 0 b = 0 c = x
 2 a = 0 b = 0 c = 0
 3 a = 0 b = 1 c = 0
 4 a = 0 b = 0 c = 0
 5 a = 0 b = 0 c = 1
 6 a = 1 b = 1 c = 1
 7 a = 0 b = 0 c = 1

Example - tri //三态线： 0， 1 ， Z


  1 module test_tri();
  2 
  3 tri a;
  4 reg b, c;
  5 
  6 assign a = (b) ? c : 1'bz;
  7 
  8 initial begin
  9   $monitor("%g a = %b b = %b c = %b", $time, a, b, c);
 10   b  = 0;
 11   c  = 0;
 12    #1  b = 1;
 13    #1  b = 0;
 14    #1  c = 1;
 15    #1  b = 1;
 16    #1  b = 0;
 17    #1  $finish;
 18 end
 19 
 20 endmodule

You could download file test_tri.v here

Simulator Output

 0 a = z b = 0 c = 0
 1 a = 0 b = 1 c = 0
 2 a = z b = 0 c = 0
 3 a = z b = 0 c = 1
 4 a = 1 b = 1 c = 1
 5 a = z b = 0 c = 1

Example - trireg //三态reg ， X， 0， 1, 驱动为Z时，保持上次状态


  1 module test_trireg();
  2 
  3 trireg a;
  4 reg b, c;
  5 
  6 assign a = (b) ? c : 1'bz;
  7 
  8 initial begin
  9   $monitor("%g a = %b b = %b c = %b", $time, a, b, c);
 10   b  = 0;
 11   c  = 0;
 12    #1  b = 1;
 13    #1  b = 0;
 14    #1  c = 1;
 15    #1  b = 1;
 16    #1  b = 0;
 17    #1  $finish;
 18 end
 19 
 20 endmodule

You could download file test_trireg.v here

Simulator Output

 0 a = x b = 0 c = 0
 1 a = 0 b = 1 c = 0
 2 a = 0 b = 0 c = 0
 3 a = 0 b = 0 c = 1
 4 a = 1 b = 1 c = 1
 5 a = 1 b = 0 c = 1

Registers store the last value assigned to them until another assignment statement changes their value.
Register存储上一次的赋值，只到有新的赋值改变它。
Registers represent data storage constructs.
Register代表以一种数据存储结构。
You can create regs arrays called memories.
你可以创建reg的数组称之为Memory。
register data types are used as variables in procedural blocks.
寄存器数据类型作为变量用在过程模块中
A register data type is required if a signal is assigned a value within a procedural block
在一个过程模块中，一个信号要赋值，则需要一个寄存器数据类型
Procedural blocks begin with keyword initial and always.
过程块以关键字initial 或者always 开头。

Data Types	Functionality
reg	Unsigned variable //无符号变量
integer	Signed variable - 32 bits //32-bit 有符号变量
time	Unsigned integer - 64 bits //64-bit 无符号数
real	Double precision floating point variable //双精度浮点变量

Note : Of all register types, reg is the one which is most widely used

注意：所有的寄存器类型中， reg是最常用的一种数据类型。

Strings //字符串

A string is a sequence of characters enclosed by double quotes and all contained on a single line.

一个字符串string是一个括在一对双引号的字符序列，在同一行上。

Strings used as operands in expressions and assignments are treated as a sequence of eight-bit ASCII values, with one eight-bit ASCII value representing one character.

用作表达式中或者赋值语句中的字符串string被当作一系列的8-bit的字符的ASCII码值的序列，（8-bit的ASCII值表示一个字符）。

To declare a variable to store a string, declare a register large enough to hold the maximum number of characters the variable will hold.

声明一个存储一个字符串的变量，要声明一个足够大的寄存器来容纳这个变量所能包含的最大字符个数。

Note that no extra bits are required to hold a termination character; Verilog does not store a string termination character. Strings can be manipulated using the standard operators.

注意，不需要额外的位来存储字符串的结束字符，在Verilog HDL 不存储字符串的结束字符。字符串可以用标准操作符操纵。

When a variable is larger than required to hold a value being assigned, Verilog pads the contents on the left with zeros after the assignment. This is consistent with the padding that occurs during assignment of non-string values.

当一个变量的容量比一个被赋值的值的size大，Verilog HDL将用0进行左填充。这和非string类型的变量的赋值是一致的。

Certain characters can be used in strings only when preceded by an introductory character called an escape character. The following table lists these characters in the right-hand column together with the escape sequence that represents the character in the left-hand column.

字符串中的某些特殊字符，引导字符，也称转义字符。下面这个表中展示了所有的转义字符。

Special Characters in Strings //字符串中的特殊字符

Character	Description
\n	New line character
\t	Tab character
\\	Backslash (\) character
\"	Double quote (") character
\ddd	A character specified in 1-3 octal digits (0 <= d <= 7)
%%	Percent (%) character

Example 字符串赋值举例


  1 //-----------------------------------------------------
  2 // Design Name : strings
  3 // File Name   : strings.v
  4 // Function    : This program shows how string
  5 //               can be stored in reg
  6 // Coder�      : Deepak Kumar Tala
  7 //-----------------------------------------------------
  8 module strings();
  9 // Declare a register variable that is 21 bytes
 10 reg [8*21:0] string ;
 11 
 12 initial begin
 13   string = "This is sample string";
 14   $display ("%s \n", string);
 15 end
 16 
 17 endmodule

You could download file strings.v here

  This is sample string

the original above link:http://www.asic-world.com/verilog/syntax3.html

wzb56

关注

0
点赞
踩
0

收藏

觉得还不错? 一键收藏
0
评论
Verilog HDL Syntax And Semantics Part-III

Hierarchical Identifiers //层次型的标识符 Hierarchical path names are based on the top module identifier followed by module instant identifiers, separated by periods.层次性的路径名是上层模块的标识符后跟着模块标识符，使
复制链接

扫一扫