Verilog HDL Behavioral Modeling Part-III

		Looping Statements // 循环语句
		Looping statements appear inside procedural blocks only; Verilog has four looping statements like any other programming language. 循环语句只出现在过程块内。 Verilog HDL与其他编程语言相似有4种循环语句。
		forever  repeat while for
		The forever statement // forever 语句
		The forever loop executes continually, the loop never ends. Normally we use forever statements in initial blocks. forever循环连续执行，永远不会结束。通常，我使用forever语句在initial块中。
		syntax : forever < statement >  //forever的语法格式
		One should be very careful in using a forever statement: if no timing construct is present in the forever statement, simulation could hang. The code below is one such application, where a timing construct is included inside a forever statement. 使用一个forever语句时，要小心：如果在一个forever语句中没有时间性的构造，仿真将将中断。下面的代码就是一个foever的应用，在forever的语句中有一个时间性的构造。
		Example - Free running clock generator //自由运行时钟产生器
		1 module forever_example (); 2 3 reg clk; 4 5 initial begin 6 #1 clk = 0; 7 forever begin 8 #5 clk = ! clk; 9 end 10 end 11 12 initial begin 13 $monitor ("Time = %d clk = %b",$time, clk); 14 #100 $finish; 15 end 16 17 endmodule You could download file forever_example.v here
		The repeat statement //repeat 语句
		The repeat loop executes < statement > a fixed < number > of times. repeat语句执行<statement>语句一个指定的<number> 次。
		syntax : repeat (< number >) < statement >  //repeat语句的语法格式
		Example- repeat // repeat 举例
		1 module repeat_example(); 2 reg [3:0] opcode; 3 reg [15:0] data; 4 reg temp; 5 6 always @ (opcode or data) 7 begin 8 if (opcode == 10) begin 9 // Perform rotate 10 repeat (8) begin 11 #1 temp = data[15]; 12 data = data << 1; 13 data[0] = temp; 14 end 15 end 16 end 17 // Simple test code 18 initial begin 19 $display (" TEMP DATA"); 20 $monitor (" %b %b ",temp, data); 21 #1 data = 18'hF0; 22 #1 opcode = 10; 23 #10 opcode = 0; 24 #1 $finish; 25 end 26 27 endmodule You could download file repeat_example.v here
		The while loop statement  //while循环语句
		The while loop executes as long as an < expression > evaluates as true. This is the same as in any other programming language. while循环在<expression>为真时，执行。 这一点和任何其他的编程语言是一致。
		syntax : while (< expression >) < statement >  //while循环的语法格式
		Example- while //while循环举例
		1 module while_example(); 2 3 reg [5:0] loc; 4 reg [7:0] data; 5 6 always @ (data or loc) 7 begin 8 loc = 0; 9 // If Data is 0, then loc is 32 (invalid value) 10 if (data == 0) begin 11 loc = 32; 12 end else begin 13 while (data[0] == 0) begin 14 loc = loc + 1; 15 data = data >> 1; 16 end 17 end 18 $display ("DATA = %b LOCATION = %d",data,loc); 19 end 20 21 initial begin 22 #1 data = 8'b11; 23 #1 data = 8'b100; 24 #1 data = 8'b1000; 25 #1 data = 8'b1000_0000; 26 #1 data = 8'b0; 27 #1 $finish; 28 end 29 30 endmodule You could download file while_example.v here
		The for loop statement  // for 循环语句
		The for loop is the same as the for loop used in any other programming language. for循环和其他任何编程语言中的for循环是一样的。
		Executes an < initial assignment > once at the start of the loop.  // 在loop开始时，只执行<initial assignment>语句一次； Executes the loop as long as an < expression > evaluates as true. //当只要<expression>语句为真的话，执行循环； Executes a < step assignment > at the end of each pass through the loop. //在每次循环结束后，执行 <step assignment语句。
		syntax : for (< initial assignment >; < expression >, < step assignment >) < statement > //for循环语句的语法格式
		Note : verilog does not have ++ operator as in the case of C language. 注意：Verilog HDL中没有像C语言中的++一样的操作符。
		Example - For // for循环举例
		1 module for_example(); 2 3 integer i; 4 reg [7:0] ram [0:255]; 5 6 initial begin 7 for (i = 0; i < 256; i = i + 1) begin 8 #1 $display(" Address = %g Data = %h",i,ram[i]); 9 ram[i] <= 0; // Initialize the RAM with 0 10 #1 $display(" Address = %g Data = %h",i,ram[i]); 11 end 12 #1 $finish; 13 end 14 15 endmodule You could download file for_example.v here

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