SystemVerilog------2011新解

In 2005 there were separate standards for Verilog and SystemVerilog which are merged here with SystemVerilog 2009. There are 30+ noticeable new constructs and 25+ system task are introduced in SystemVerilog 2009.

I listed out following new constructs which are added in SV-2009.



timeunit and timeprecision

You can specify timeunit and timeprecision inside the module with single keyword.


module E (...);
   timeunit 100ps / 10fs ;  // timeunit with optional second argument
   ...
endmodule

(Ch. 3.14.2.2 of LRM)


checker - endchecker

The checker is specifically created to encapsulate assertions. It can be added with the modeling code and can be instantiationed. Formal arguments of checker are inputs.

(Ch. 17)

checker my_check1 ( logic test_sig );
  a1 :  assert  property  (p (test_sig ));
  c1 :  cover  property  (!test_sig ## 1 test_sig );
endchecker : my_check1

global clocking

Global clocking block is declared as the global clocking block for an entire elaborated SystemVerilog model.

global clocking  @(clk1 or clk2 ); 
endclocking

(Ch. 14.14)

Printing format

%p - displays as an assignment format.

(Ch 21.2.1.2)


%x - displays in hexadecimal format.

(Ch 21.2.1.2)

edge

It is equivalent to posedge+negedge

(Ch. 31.5)

let

This local score compiler directive replaces the other test macro like `define. A let construct may be instantiated in other expressions.
let declarations can be used for customization and can replace the text macros in many cases.

let check_grant (a , b )  =  assert ( a ## 2 b )  );
check_grant (req , gnt );
(Ch. 11.13)

localparam in ANSI style header
module driver #( parameter  AWIDTH  =  8 ,
                 parameter  DWIDTH  =  8 ,
                 localparam  PORT = 1  >>  data
               );
(Ch. 22.2.3)

unique0

Keyword unique will issue a violation report if no condition matches. while keyword unique0 will not issue a violation report if no condition matches.

(Ch. 12.4.2)

Associative array size()

size() method is introduced to return number of entries in associative array like num() method.

(Ch. 7.9.1)

Queue delete()

Now you can pass specific index number inside the delete function to delete that particular index. If index is not specified then it will delete entire Q.

(Ch. 7.10.2)

Bit select and part select of an expression
Instead of ...
assign t =  (a & b )  |  (c & d );
assign val = t [ 7 : 4 ];

you can do...

assign val =  {(a & b )  |  (c & d )}[ 7 : 4 ];
(Ch. 7.2.1)

Import package into design
package bit_pkg ;
   bit clk ;
   bit reset ;
endpackage

module dut (
   input bit_pkg ::reset rst ;
   input bit_pkg ::clk clock ;
   ...
endmodule


Packet chaining, automatic package and multiple package export is also introduced in SV-2009.

(Ch. 23)

pure virtual methods

SV-2009 allows to declare pure virtual methods as well as class. It must be written in abstract class & it must be only a prototype, It must not contain any statement and must with without endtask/endfunction.


virtual  class BasePacket ;
   pure  virtual  function  integer send ( bit [ 31 : 0 ]  data );  // No implementation
endclass
(Ch. 8.20)

pure constraint

It is allowd to declare pure constraint in abstract class. This must be implemented in extended class with the same constraint name.

virtual  class C ;
   pure  constraint test ;
endclass
(Ch. 18.5.2)

Time consuming functions

Using fork/join_none, now time consuming constructs can be used inside function.

function  void disp ;
fork
   # 0  $display ( "%t: This is #0" ,  $time );
   # 1  $display ( "%t: This is #1" ,  $time );
   # 3  $display ( "%t: This is #3 and A = %x" ,  $time , a );
  a <=  8'hbb ;  // It allows non-blocking assignment
   # 2  $display ( "%t: This is #2" ,  $time );
join_none
endfunction
(Ch. 9.3.2)

covergroup with sample arguments
covergroup  with  function sample ( bit a ,  int x );
   coverpoint x ;
   cross x , a ;
endgroup  : 

cg cg1 =  new ;

function  void F ( int j );
bit d ;
   ...
  cg1 .sample ( d , j );
endfunction
(Ch. 19.8.1)

weak - strong

These sequence operators are introduced to simulate assertion efficiently. Assert may produce wrong message if there is a glitch in the signal. strong require that some terminating condition happen in the future, and this includes the requirement that the property clock ticks enough time to enable the condition to happen. weak do not impose any requirement on the terminating condition, and do not require the clock to tick. If the strong or weak operator is omitted, then the evaluation of the sequence_expr depends on the assertion statement in which it is used. If the assertion statement is assert property or assume property, then the sequence_expr is evaluated as weak(sequence_expr). Otherwise, the sequence_expr is evaluated as strong(sequence_expr).

The default in SV-2005 was strong while in SV-2009 is weak unless you. specified
strong.

(Ch. 16.13)

Implies and iff properties

A property is an implies if it has the following form:

property_expr1 implies property_expr2

Above form evaluates to true if property_expr1 evaluates to true, if not then

property_expr2 evaluates to true.

A property is an iff if it has the following form:

property_expr1 iff property_expr2

A property of this form evaluates to true if, and only if, either both

property_expr1 evaluates to false and property_expr2 evaluates to false or both

property_expr1 evaluates to true and property_expr2 evaluates to true.

(Ch. 16.13)

followed-by (#-#, #=#)
property s1 ;
   ##[ 0 : 5 ] done #-#  always  !rst ;
endproperty
property s2 ;
   ##[ 0 : 5 ] done #=#  always  !rst ;
endproperty

Property s1 says that done shall be asserted at some clock tick during the first 6 clock ticks, and starting from one of the clock ticks when done is asserted, rst shall always be low. Property s2 says that done shall be asserted at some clock tick during the first 6 clock ticks, and starting the clock tick after one of the clock ticks when done is asserted, rst shall always be low.

(Ch. 16.13)

The property operators

s_nexttime, s_always, s_eventually, s_until, s_until_with, and sequence operator strong are strong.
The property operators nexttime, always, until, eventually, until_with, and sequence operator
weak are weak.


nexttime and s_nexttime
// if the clock ticks once more, then a shall be true at the next clock tick
property s1 ;
  nexttime a ;
endproperty
// the clock shall tick once more and a shall be true at the next clock tick.
property s2 ;
  s_nexttime a ;
endproperty
(Ch. 16.13)

always - s_always

property s1 ;
  a ## 1 b |=>  always c ;
endproperty


property s1 evaluates to true provided that if a is true at the first clock tick and b is true at the second clock tick, then c shall be true at every clock tick that follows the second.

(Ch. 16.13)

until - until_with - s_until - s_until_with

property s1 ;
 a until b ;
endproperty

property p3 ;
 a until_with b ;
endproperty


Property s1 evaluates to true if, and only if, a is true at every clock tick beginning with the starting clock tick of the evaluation attempt and continuing
until, but not necessarily including, a clock tick at which b is true.

(Ch. 16.13)

The property p3 evaluates to true provided that a is true at every clock tick beginning with the starting clock tick of the evaluation attempt and continuing
until and including a clock tick at which b is true.

(Ch. 16.13)

eventually - s_eventually
property s1 ;
  s_eventually a ;
endproperty

The property s1 evaluates to true if, and only if, there exists a current or future clock tick at which a is true.

(Ch. 16.13.13)

not - accept_on - reject_on - sync_accept_on - sync_reject_on
property p ;  (accept_on (a ) s1 );  endproperty

If a becomes true during the evaluation of s1, then p evaluates to true.


property p ;  (reject_on (b ) s2 );  endproperty

If b becomes true during the evaluation of s2 then p evaluates to false.


property p ;  not  (reject_on (b ) s2 );  endproperty

not inverts the effect of operator, so if b becomes true during the evaluation of s2 then p evaluates to true.

(Ch. 16.13.14)

case

case can be used inside the property.

(Ch. 16.13.16)

restrict

It is constraint to the formal verification tool to do not check the property.


untyped

It is allowed to use untyped datatype inside properties.


(Deferred assertion )  assert  # 0  -  assume  # 0  -  cover  # 0

Deferred immediate assertion evaluates after signal have stabilized in a time step.


Shortcut operators
##[+] is equivalent to ##[ 1 :$ ]
##[*] is equivalent to ##[ 0 :$ ]
<signal >[+] is equivalent to <signal >[* 1 :$ ]
<signal >[*] is equivalent to <signal >[* 0 :$ ]
(Ch. 16.7)

`define

you can pass default value in define macro.

`define  MACRO1 (a = 5 )  $display (a );
(Ch. 22.5)

`undefineall

It undefines all the defined test macro which is previously declared.

`define  FPGASIM
`define  GATESIM
module ...
....
....
endmodule
`undefineall
(Ch. 22.5)

`begin_keywords and `end_keywords

It is used to specify reserved keywords, it will give an error if implementain does not matched with version_specifier. e.g if you have specified "1800-2009" then all the previous versions of Verilog/SystemVerilog keywords can be used but if you have specified "1800-2005" then those keywords which are introduced specifically in SV-2009 those can not be used.

(Ch. 22.14)

FILE name and LINE numbers

It keeps track of the filenames of SystemVerilog source files and line nunbers in the files. which can be helpfull to source error messages and the file name. `__FILE__ expands to the name of the current input file, in the form of a string literal constant. This is the path by which the compiler opened the file, not  the short name specified in `include or as the command line argument. `__LINE__ expands to the current input line number, in the form of a decimal

integer constant .

$display ( "Internal error: null handle at %s, line %d." , `__FILE__ ,  `__LINE__ );

file path and line number will be return which contain above message.

(Ch. 22.12, 22.13)

SYSTEM TASK


$syatem - allows operation system commands.

(Ch 20.18.1)


$global_clock returns the event statement which is written global clocking block declaration. Here it will return "clk1 or clk2".

(Ch. 14.14)


$sformatf - this system function returns the message into string. Thus string can be passed into valid function.
$fatel - $error - $warning - $info can be used outside assertion.
$assertpasson - enable execution of pass statement.
$assertpassoff - stop execution of pass statement.  
$assertfailon - enable execution of pass statement.
$assertfailoff - stop execution of fail statement.
$assertnonvacuouson - enable execution of pass statement when assertion is vacuous.
$assertvacuousoff - stop execution of pass statement when assertion is non vacuous.

(Ch 20.14, 16.15.8)

$changed

It detect changes in values between two adjscent clock tics.

(Ch 20.13)

$past_gclk  -  $rose_gclk  -  $fell_gclk  -  $stable_gclk  -  $changed_gclk

It will give past sampled value of the signal with respect to global clock.

(Ch 20.13)

$future_gclk  -  $rosing_gclk  -  $falling_gclk  -  $steady_gclk  -  $changing_gclk

It will give future sampled value of the signal with respect to global clock.

(Ch 20.13, 16.15.8)

$inferred_clock  -  $inferred_disable  -  $inferred_enable

These system function are available to query assertion

(Ch. 16.15.7)

Protected envelopes

It specify a region of text that shall be transformed prior to analysis by the source language processor.

(Ch. 34)


Still there could be many enhancement behind the curtain. It always GOOD to KNOW more. Your feedback/input/thought are welcomed which can help me to update contain. Reach me at mail2ajshah@gmail.com



from： http://testbench.in/SystemVerilog_2009_enhancements.html

See here for my complete list of the likely SystemVerilog 2009 design enhancements.  (Disclaimer: All of these are subject to change until after the balloting process is completed, but I doubt they will actually change much.)

Associated with each item is a link  into a publicly readable database.  The proposals are in the Attached Files sections.

2digg

Some highlights

• default parameter values optional
• selects on (concatenated) expressions, e.g., {a+b}[4:0]
• logical equivalence (<->) and implication (->) operators
• default values for macro args
• default input values for module/interface ports
• 0-delay-glitch-free semantics of unique/unique0/priority case/if
• ‘let’ name binding construct
• package import declarations in module/interface headers

To me, ‘let’ is the most interesting of these. For example, you could use it to add a ‘rot(v,n)’ syntax for barrel shifting ‘v’ by ‘n’

let rot(v, n) = {2{v}} << n >> $bits(v);

Here’s an example combining ‘let’ and selects on expressions.  Suppose you want to select bits from an expression that evaluates to a bit-stream type , but not a packed type, as required for selects on expression.  Define a ‘let’ to bit-stream cast them into a simple bit-vector type

let pack (x) = type($bits(x)’(0))’(x) ;

and select away, for example

{ pack(expression) } [N-1:0]

And to force an arithmetic expression to be evaluated in a self-determined context, you could use the following ‘let’

let selfd(x) = type(x)’(x) ;

FYI — there are also some significant enhancements to the assertions sublanguage.