[Branch Prediction]处理器分支预测文献笔记(4)

[文献名] Evers, M., S.J. Patel, R.S. Chappell, and Y.N. Patt. “An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work.” In The 25th Annual International Symposium on Computer Architecture, 1998. Proceedings, 52–61, 1998. doi:10.1109/ISCA.1998.694762.

[相关观点]

1.To build high performance microprocessors, accurate branch prediction is required

2.分析二级预测器性能好的原因是程序中分支存在相关性。

 

[文献名] Juan, T., S. Sanjeevan, and J.J. Navarro. “Dynamic History-Length Fitting: A Third Level of Adaptivity for Branch Prediction.” In The 25th Annual International Symposium on Computer Architecture, 1998. Proceedings, 155–66, 1998. doi:10.1109/ISCA.1998.694771.

[相关观点]

1.the history length used for a particular code has a significant impact on predictor performance

2.历史长度应该适应程序才能发挥出性能。In the previous section it has been shown that each code requires a specific amount of history to give the best results

 

[文献名] Akkary, Haitham, Srikanth T. Srinivasan, and Konrad Lai. “Recycling Waste: Exploiting Wrong-Path Execution to Improve Branch Prediction.” In Proceedings of the 17th Annual International Conference on Supercomputing, 12–21. ICS ’03. New York, NY, USA: ACM, 2003. doi:10.1145/782814.782819.

[相关观点]

1. 利用错误分支信息改进预测。

 

 

Figure 2 shows one possible implementation of branch recycling.A two-level adaptive branch recycling predictor (BRP) and a branch recycling cache (BRC) supplement a conventional branch predictor (BP). The BRP uses a prediction algorithm, similar to a gshare branch predictor [13], to identify correlating branch instances. The first level uses a short history of the last m branches encountered on the correct path, as well as the addresses of two branches: the mispredicted branch (MB) that caused the wrong-path execution, and the correct-path candidate branch (CB)being predicted. The outcomes of the last m branches are shifted into a branch history register (BHR) [19]. The address of MB is shifted left by n bits, where n = m/2. The BHR, m bits from CB address, and m bits from the shifted MB address are XORed together and the result is used to index an array of state machines.

The state machines are implemented as 2-bit saturating counters.When the counter value is larger than 1, the branch is predicted to correlate with its wrong-path counterpart. The WP outcome is then selected to be the prediction instead of the prediction from BP.

 

2.30%的改进

 

[文献名] Palermo, G., M. Sam, C. Silvan, V. Zaccari, and R. Zafalo. “Branch Prediction Techniques for Low-Power VLIW Processors.” In Proceedings of the 13th ACM Great Lakes Symposium on VLSI, 225–28. GLSVLSI ’03. New York, NY, USA: ACM, 2003. doi:10.1145/764808.764866.

[相关观点]

1.Only if a branch is detected in the decompression buffer, the branch prediction logic is activated, thus reducing the number of accesses to the branch predictor and consequently the related power dissipation

2.When operations are fetched from the instruction cache and stored in the decompression buffer (Instruction Buffer), a Branch Detector (BD) partially pre-decodes the instructions to find a possible branch. The implementation of the BD is dependent on the encoding of the branch instruction. If a branch is detected, its PC is sent to the branch prediction block in order to activate the branch prediction, otherwise the instructions in the decompression buffer are sequentially executed.

 

[文献名] Monchiero, M., G. Palermo, M. Sami, C. Silvano, V. Zaccaria, and R. Zafalon. “Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors.” In Proceedings of the 14th ACM Great Lakes Symposium on VLSI, 440–43. GLSVLSI ’04. New York, NY, USA: ACM, 2004. doi:10.1145/988952.989058.

[相关观点]

利用指令提示实现低功耗。