IC 设计流程

Step 1: Prepare an Requirement Specification

Step 2: Create an Micro-Architecture Document.

Step 3: RTL Design & Development of IP's

Step 4: Functional verification all the IP's/Check whether the RTL is free fromLinting Errors/Analyze whether the RTL is Synthesis friendly.Step 4a: Perform Cycle-based verification(Functional) to verify the protocolbehaviour of the RTLStep 4b: Perform Property Checking , to verify the RTL implementation and thespecification understanding is matching.

Step 5: Prepare the Design Constraints file (clockdefinitions(frequency/uncertainity/jitter),I/O delay definitions, Output pad loaddefinition, Design False/Multicycle-paths) to perform Synthesis, usually called as anSDC synopsys_constraints, specific to synopsys synthesis Tool (design-compiler)

Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(forwhich synthesis needs to be targeted for, which has the functional/timing informationavailable for the standard-cell library and the wire-load models for the wires based onthe fanout length of the connectivity), RTL files and the Design Constraint files, Sothat the Synthesis tool can perform the synthesis of the RTL files and map andoptimize to meet the design-constraints requirements. After performing synthesis, as apart of the synthesis flow, need to build scan-chain connectivity based on theDFT(Design for Test) requirement, the synthesis tool (Test-compiler), builds thescan-chain.

7: Check whether the Design is meeting the requirements(Functional/Timing/Area/Power/DFT) after synthesis.

Step 7a: Perform the Netlist-level Power Analysis, to know whether the design ismeeting the power targets.

Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check whetherthe design is meeting the functional requirements.

Step 7c: Perform Formal-verification between RTL vs Synthesized Netlist to confirmthat the synthesis Tool has not altered the functionality.

Step 7d: Perform STA(Static Timing Analysis) with the SDF(Standard Delay Format)file and synthesized netlist file, to check whether the Design is meeting thetiming-requirements.

Step 7e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain isbuilt based on the DFT requirement.

Step 8: Once the synthesis is performed the synthesized netlist file(VHDL/Verilogformat) and the SDC (constraints file) is passed as input files to the Placement andRouting Tool to perform the back-end Actitivities.

Step 9: The next step is the Floor-planning, which means placing the IP's based on theconnectivity,placing the memories, Create the Pad-ring, placing thePads(Signal/power/transfer-cells(to switch voltage domains/Corner pads(properaccessibility for Package routing), meeting the SSN requirements(SimultaneousSwitching Noise) that when the high-speed bus is switching that it doesn't create anynoise related acitivities, creating an optimised floorplan, where the design meets theutilization targets of the chip.

Step 9a : Release the floor-planned information to the package team, to perform thepackage feasibility analysis for the pad-ring .