//----------------------------------------------顶层
module VGA_all_top
(
input refclk,
input rst_n,
input in_top,
output vs,
output hs,
output [4:0]r,
output [5:0]g,
output [4:0]b,
output out_tx
);
wire [7:0]out_top;
uart_top//----uart_RX
uart_top_inst
(
.refclk(refclk),
.rst_n(rst_n),
.in_top(in_top),
.out_top(out_top),
.out_stop(out_stop),
.clk(uart_clk),
.rst(uart_rst)
);
uart_tx//--------uart_TX
uart_tx_inst
(
.refclk(refclk),
.rst_n(rst_n),
.in_rx(out_top),
.in_stop(out_stop),
.out_tx(out_tx)
);
wire [23:0]out_pin;
wire [12:0]add_w;
/*pinjie
pinjie_inst*/
pinjie_FZ90//-----RGB数据拼接,写地址翻转90度
pinjie_FZ90_inst
(
.clk(uart_clk),
.rst(uart_rst),
.in(out_top),
.in_stop(out_stop),
.out(out_pin),
.wradd(add_w),
.wren(wren)
);
wire [12:0]add_r;
wire [9:0]cont_v;
wire [10:0]cont_h;
rden//---------------读使能,读地址
rden_inst
(
.refclk(refclk),
.rst_n(rst_n),
.en(en),
.cont_v(cont_v),
.cont_h(cont_h),
.wradd(add_w),
.rdadd(add_r),
.rden(rden)
);
wire [23:0]q_ram;
wire [4:0]q,q2;
wire [5:0]q1;
ram ram_inst (//-----------24位宽,4095深度ram
.clock ( refclk ),
.data ( out_pin ),
.rdaddress ( add_r ),
.rden ( rden ),
.wraddress ( add_w ),
.wren ( wren ),
.q ( q_ram )
);
assign q=q_ram[7:3],q1=q_ram[15:10],q2=q_ram[23:19];
VGA_top
VGA_top_inst
(
.refclk(refclk),
.rst_n(rst_n),
.in_top(q),
.in_top1(q1),
.in_top2(q2),
.vs(vs),
.hs(hs),
.r(r),
.g(g),
.b(b),
.en(en),
.cont_h(cont_h),
.cont_v(cont_v)
);
endmodule
//-----------------------------------------------------------uart
module uart_top
(
input refclk,
input rst_n,
input in_top,
output [7:0]out_top,
output out_stop,
output clk,
output rst
);
pll_5m pll_5m_inst
(
.areset ( ~rst_n ),
.inclk0 ( refclk ),
.c0 ( clk ),
.locked ( rst )
);
pd
pd_inst
(
.clk(clk),
.rst(rst),
.in_top(in_top),
.out_pd_starte(out_pd_starte)
);
ztj
ztj_inst
(
.clk(clk),
.rst(rst),
.in_top_z(in_top),
.in_en(out_pd_starte),
.out_stop(out_stop),
.out_ztj(out_top)
);
endmodule
module pd
(
input clk,
input rst,
input in_top,
output out_pd_starte
);
reg vs_pd;
wire neg;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs_pd<=1'b0;
else
vs_pd<=in_top;
end
assign neg=(~in_top)&vs_pd;
//----------------------------------
reg vs_pd1;
reg [7:0]cont;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont<=1'b0;
else if(cont==8'd180)//9*PI
cont<=1'b0;
else if(vs_pd1==1'b1)
cont<=cont+1'b1;
end
always@(posedge clk )
begin
if(~rst)
vs_pd1 <=1'b0;
else if(neg==1'b1)
vs_pd1 <=1'b1;
else if(cont==8'd180)
vs_pd1<=1'b0;
end
reg vs_pd2;
always@(posedge clk )
begin
if(~rst)
vs_pd2 <=1'b0;
else if(vs_pd1 ==1'b1)
vs_pd2 <=1'b0;
else
vs_pd2<=neg;
end
assign out_pd_starte=vs_pd2;
endmodule
module ztj
(
input clk,
input rst,
input in_top_z,
input in_en,
output [7:0]out_ztj,
output out_stop
);
parameter IDLE=4'b0000;
parameter start=4'b0001;
parameter bit0=4'b0010;
parameter bit1=4'b0011;
parameter bit2=4'b0100;
parameter bit3=4'b0101;
parameter bit4=4'b0110;
parameter bit5=4'b0111;
parameter bit6=4'b1000;
parameter bit7=4'b1001;
parameter stop=4'b1010;
parameter PI=5'd19-1;
reg [4:0]cont;
always@(posedge clk)
begin
if(~rst)
cont<=5'd0;
else if(in_en==1'b1)
cont<=5'd0;
else if(cont==PI)
cont<=5'd0;
else
cont<=cont+5'd1;
end
reg [3:0]cont_z;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont_z<=4'd0;
else if(in_en==1'b1)
cont_z<=4'd0;
else if((cont_z==4'd10)&&(cont==PI))
cont_z<=4'd0;
else if(cont==PI-1)
cont_z<=cont_z+4'd1;
end
//----------------------------------------------
reg [7:0]out;//
reg [3:0]current_state;
reg [3:0]next_state;
always@(posedge clk or negedge rst)
begin
if(~rst)
current_state<=IDLE;
else
current_state<=next_state;
end
always@(*)
begin
next_state=IDLE;
case(current_state)
IDLE:if(in_en==1'b1)
next_state=start;
else
next_state=IDLE;
start:if(cont_z==4'd1)
next_state=bit0;
else
next_state=start;
bit0:if(cont_z==4'd2)
next_state=bit1;
else
next_state=bit0;
bit1:if(cont_z==4'd3)
next_state=bit2;
else
next_state=bit1;
bit2:if(cont_z==4'd4)
next_state=bit3;
else
next_state=bit2;
bit3:if(cont_z==4'd5)
next_state=bit4;
else
next_state=bit3;
bit4:if(cont_z==4'd6)
next_state=bit5;
else
next_state=bit4;
bit5:if(cont_z==4'd7)
next_state=bit6;
else
next_state=bit5;
bit6:if(cont_z==4'd8)
next_state=bit7;
else
next_state=bit6;
bit7:if(cont_z==4'd9)
next_state=stop;
else
next_state=bit7;
stop:if(cont_z==4'd10)
next_state=IDLE;
else
next_state=stop;
default:next_state=IDLE;
endcase
end
//-------------------------------------------
reg vs_stop;
always@(posedge clk)
begin
if(~rst)
vs_stop<=1'b0;
else if((cont==(PI+1)/2)&&(current_state==stop))
vs_stop<=1'b1;
else
vs_stop<=1'b0;
end
assign out_stop=vs_stop;
//-------------------------------------------
reg vs_cont;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs_cont<=1'b0;
else if(cont==(PI+1)/2)
vs_cont<=1'b1;
else
vs_cont<=1'b0;
end
//----------------------------------------
reg vs_tb1;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs_tb1<=1'b0;
else
vs_tb1<=in_top_z;
end
reg vs_tb2;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs_tb2<=1'b0;
else
vs_tb2<=vs_tb1;
end
reg vs_tb;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs_tb<=1'b0;
else
vs_tb<=vs_tb2;
end
//---------------------------------------
always@(posedge clk or negedge rst)
begin
if(~rst)
out<=8'b0;
else if(vs_cont<=1'b1)
begin
case(next_state)
bit0:
out[0]<=vs_tb;
bit1:
out[1]<=vs_tb;
bit2:
out[2]<=vs_tb;
bit3:
out[3]<=vs_tb;
bit4:
out[4]<=vs_tb;
bit5:
out[5]<=vs_tb;
bit6:
out[6]<=vs_tb;
bit7:
out[7]<=vs_tb;
endcase
end
else if(in_en==1'b1)
out<=8'd0;
end
assign out_ztj=out;
endmodule
module uart_tx
(
input refclk,
input rst_n,
input [7:0]in_rx,
input in_stop,
output out_tx
);
pll_5m pll_5m_inst
(
.areset ( ~rst_n ),
.inclk0 ( refclk ),
.c0 ( clk ),
.locked ( rst )
);
ztj_tx
ztj_tx_inst
(
.clk(clk),
.rst(rst),
.in(in_rx),
.tx_en(in_stop),
.out_tx(out_tx)
);
endmodule
module ztj_tx
(
input clk,
input rst,
input [7:0]in,
input tx_en,
output out_tx
);
parameter IDLE=4'b0000;
parameter start=4'b0001;
parameter bit0=4'b0010;
parameter bit1=4'b0011;
parameter bit2=4'b0100;
parameter bit3=4'b0101;
parameter bit4=4'b0110;
parameter bit5=4'b0111;
parameter bit6=4'b1000;
parameter bit7=4'b1001;
parameter stop=4'b1010;
parameter PI=5'd19-1;
reg [4:0]cont;
always@(posedge clk)
begin
if(~rst)
cont<=5'd0;
else if(tx_en==1'b1)
cont<=5'd0;
else if(cont==PI)
cont<=5'd0;
else
cont<=cont+5'd1;
end
reg [3:0]cont_z;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont_z<=4'd0;
else if(tx_en==1'b1)
cont_z<=4'd0;
else if((cont_z==4'd10)&&(cont==PI))
cont_z<=4'd0;
else if(cont==PI-1)
cont_z<=cont_z+4'd1;
end
//----------------------------------------------
reg out_ztj;
reg [3:0]current_state;
reg [3:0]next_state;
always@(posedge clk or negedge rst)
begin
if(~rst)
current_state<=IDLE;
else
current_state<=next_state;
end
always@(*)
begin
next_state=IDLE;
case(current_state)
IDLE:if(tx_en==1'b1)
next_state=start;
start:if(cont_z==4'd1)
next_state=bit0;
else
next_state=start;
bit0:if(cont_z==4'd2)
next_state=bit1;
else
next_state=bit0;
bit1:if(cont_z==4'd3)
next_state=bit2;
else
next_state=bit1;
bit2:if(cont_z==4'd4)
next_state=bit3;
else
next_state=bit2;
bit3:if(cont_z==4'd5)
next_state=bit4;
else
next_state=bit3;
bit4:if(cont_z==4'd6)
next_state=bit5;
else
next_state=bit4;
bit5:if(cont_z==4'd7)
next_state=bit6;
else
next_state=bit5;
bit6:if(cont_z==4'd8)
next_state=bit7;
else
next_state=bit6;
bit7:if(cont_z==4'd9)
next_state=stop;
else
next_state=bit7;
stop:if(cont_z==4'd10)
next_state=IDLE;
else
next_state=stop;
default:next_state=IDLE;
endcase
end
//-------------------------------------------
always@(posedge clk or negedge rst)
begin
if(~rst)
out_ztj<=1'b1;
else
case(next_state)
IDLE:
out_ztj<=1'b1;
start:
out_ztj<=1'b0;
bit0:
out_ztj<=in[0];
bit1:
out_ztj<=in[1];
bit2:
out_ztj<=in[2];
bit3:
out_ztj<=in[3];
bit4:
out_ztj<=in[4];
bit5:
out_ztj<=in[5];
bit6:
out_ztj<=in[6];
bit7:
out_ztj<=in[7];
stop:
out_ztj<=1'b1;
default:out_ztj<=1'b1;
endcase
end
assign out_tx=out_ztj;
endmodule
//---------------------------------------------------------拼接,写使能,写地址
module pinjie
(
input clk,
input rst,
input [7:0]in,
input in_stop,
output [23:0]out,
output [12:0]wradd,
output wren
);
reg [1:0]cont;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont<=2'd0;
else if(cont==2'd2&&in_stop==1'b1)
cont<=2'd0;
else if(in_stop==1'b1)
cont<=cont+1'b1;
end
reg [7:0]a1,a2,a3;
always@(posedge clk or negedge rst)
begin
if(~rst)
begin
a1<=8'd0;
a2<=8'd0;
a3<=8'd0;
end
else if(cont==2'b0&&in_stop==1'b1)
a1<=in;
else if(cont==2'd1&&in_stop==1'b1)
a2<=in;
else if(cont==2'd2&&in_stop==1'b1)
a3<=in;
end
reg vs;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs<=1'b0;
else if(cont==2'd2&&in_stop==1'b1)
vs<=1'b1;
else
vs<=1'b0;
end
reg [23:0]a4;
always@(posedge clk or negedge rst)
begin
if(~rst)
a4<=24'd0;
else if(vs==1'b1)
begin
a4[7:0]<=a1;
a4[15:8]<=a2;
a4[23:16]<=a3;
end
end
assign out=a4;
assign vs1=vs;
//--------------------------------------wr
reg [12:0]cont_w;
reg wr;
always@(posedge clk or negedge rst)
begin
if(~rst)
wr<=1'b0;
else if(vs1==1'b1)
wr<=1'b1;
else if(cont_w==13'd4095)
wr<=1'b0;
end
always@(posedge clk or negedge rst)
begin
if(~rst)
cont_w<=13'd0;
else
begin
if(cont_w==13'd4095&&vs==1'b1)
cont_w<=13'd0;
else if(vs1==1'b1&&wr==1'b1)
cont_w<=cont_w+1'b1;
end
end
assign wradd=cont_w;
assign wren=wr;
endmodule
//---------------------------------------拼接,写使能,写地址,翻转90度
module pinjie_FZ90
(
input clk,
input rst,
input [7:0]in,
input in_stop,
output [23:0]out,
output [12:0]wradd,
output wren
);
reg [1:0]cont;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont<=2'd0;
else if(cont==2'd2&&in_stop==1'b1)
cont<=2'd0;
else if(in_stop==1'b1)
cont<=cont+1'b1;
end
reg [7:0]a1,a2,a3;
always@(posedge clk or negedge rst)
begin
if(~rst)
begin
a1<=8'd0;
a2<=8'd0;
a3<=8'd0;
end
else if(cont==2'b0&&in_stop==1'b1)
a1<=in;
else if(cont==2'd1&&in_stop==1'b1)
a2<=in;
else if(cont==2'd2&&in_stop==1'b1)
a3<=in;
end
reg vs;
always@(posedge clk or negedge rst)
begin
if(~rst)
vs<=1'b0;
else if(cont==2'd2&&in_stop==1'b1)
vs<=1'b1;
else
vs<=1'b0;
end
reg [23:0]a4;
always@(posedge clk or negedge rst)
begin
if(~rst)
a4<=24'd0;
else if(vs==1'b1)
begin
a4[7:0]<=a1;
a4[15:8]<=a2;
a4[23:16]<=a3;
end
end
assign out=a4;
assign vs1=vs;
//--------------------------------------wr
reg [12:0]cont_w;
reg wr;
always@(posedge clk or negedge rst)
begin
if(~rst)
wr<=1'b0;
else if(vs1==1'b1)
wr<=1'b1;
else if(cont_w==13'd4095)
wr<=1'b0;
end
//------------------------------------翻转
reg [5:0]cont_f;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont_f<=6'd0;
else if(cont_f==6'd63&&vs1==1'b1)
cont_f<=6'd0;
else if(vs1==1'b1&&wr==1'b1)
cont_f<=cont_f+1'b1;
end
reg [5:0]cont2;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont2<=6'd1;
else
begin
if(cont2==6'd63&&cont_f==6'd63&&vs1==1'b1)
cont2<=6'd1;
else if(cont_f==6'd63&&vs1==1'b1)
cont2<=cont2+1'd1;
end
end
//------------------------------------
always@(posedge clk or negedge rst)
begin
if(~rst)
cont_w<=13'd0;
else
begin
if(cont_f==6'd63&&vs1==1'b1)
cont_w<=cont2;
else if(vs1==1'b1&&wr==1'b1)
cont_w<=cont_w+7'd64;
end
end
assign wradd=cont_w;
assign wren=wr;
endmodule
//----------------------------------------------------------读使能,读地址
module rden
(
input refclk,
input rst_n,
input en,
input [9:0]cont_v,
input [10:0]cont_h,
input [12:0]wradd,
output [12:0]rdadd,
output rden
);
pll
pll_inst
(
.areset ( ~rst_n ),
.inclk0 ( refclk ),
.c0 ( clk ),
.locked ( rst )
);
//--------------------------------------rd
reg wr_stop;
always@(posedge clk or negedge rst)
begin
if(~rst)
wr_stop<=1'b0;
else if(wradd>13'd4094)
wr_stop<=1'b1;
else
wr_stop<=1'b0;
end
reg [12:0]cont;
reg en1;
always@(posedge clk or negedge rst)
begin
if(~rst)
en1<=1'b0;
else
begin
if((((11'd215<cont_h)&&(cont_h<11'd281))&&((10'd27<cont_v)&&(cont_v<10'd92)))&&(en==1'b1)&&(wr_stop<=1'b1))
en1<=1'b1;
else
en1<=1'b0;
end
end
always@(posedge clk or negedge rst)
begin
if(~rst)
cont<=13'd0;
else
begin
if(cont==13'd4095)
cont<=13'd0;
else if(en1==1'b1)
cont<=cont+1'b1;
end
end
assign rdadd=cont;
assign rden=en1;
endmodule
//----------------------------------VGA
module VGA_top
(
input refclk,
input rst_n,
input [4:0]in_top,
input [5:0]in_top1,
input [4:0]in_top2,
output vs,
output hs,
output [4:0]r,
output [5:0]g,
output [4:0]b,
output en,
output [9:0]cont_v,
output [10:0]cont_h
);
pll
pll_inst
(
.areset ( ~rst_n ),
.inclk0 ( refclk ),
.c0 ( clk ),
.locked ( rst )
);
vga
vga_inst
(
.clk(clk),
.rst(rst),
.en(en),
.vga_vs(vs),
.vga_hs(hs),
.cont_v(cont_v),
.cont_h(cont_h)
);
rgb
rgb_inst
(
.clk(clk),
.rst(rst),
.en(en),
.cont_v(cont_v),
.cont_h(cont_h),
.in_top(in_top),
.in_top1(in_top1),
.in_top2(in_top2),
.r(r),
.g(g),
.b(b)
);
endmodule
module vga
(
input clk,
input rst,
output en,
output vga_vs,
output vga_hs,
output [9:0]cont_v,
output [10:0]cont_h
);
reg [10:0]cont_hs;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont_hs<=11'd0;
else if(cont_hs==11'd1055)
cont_hs<=11'd0;
else
cont_hs<=cont_hs+1'b1;
end
reg [9:0]cont_vs;
always@(posedge clk or negedge rst)
begin
if(~rst)
cont_vs<=10'd0;
else if(cont_hs==11'd1055)
begin
if(cont_vs==10'd627)
cont_vs<=10'd0;
else
cont_vs<=cont_vs+1'b1;
end
end
assign cont_v=cont_vs;
assign cont_h=cont_hs;
reg vga_vs1;//行同步
always@(posedge clk or negedge rst)
begin
if(~rst)
vga_vs1<=1'b0;
else if(cont_vs==10'd0)
vga_vs1<=1'b1;
else if(cont_vs==10'd3)
vga_vs1<=1'b0;
end
assign vga_vs=~vga_vs1;
reg vga_hs1;//列同步
always@(posedge clk or negedge rst)
begin
if(~rst)
vga_hs1<=1'b0;
else if(cont_hs==11'd0)
vga_hs1=1'b1;
else if(cont_hs==11'd128)
vga_hs1<=1'b0;
end
assign vga_hs=vga_hs1;
//--------------------------------
reg en_vs;
always@(posedge clk or negedge rst)
begin
if(~rst)
en_vs<=1'b0;
else if(cont_vs==10'd26)
en_vs<=1'b1;
else if(cont_vs==10'd626)
en_vs<=1'b0;
end
reg en_hs;
always@(posedge clk or negedge rst)
begin
if(~rst)
en_hs<=1'b0;
else if(cont_hs==11'd215)
en_hs<=1'b1;
else if(cont_hs==11'd1015)
en_hs<=1'b0;
end
reg en1;
always@(posedge clk or negedge rst)
begin
if(~rst)
en1<=1'b0;
else if((en_vs==1'b1)&&(en_hs==1'b1))
en1<=1'b1;
else
en1<=1'b0;
end
assign en=en1;
endmodule
module rgb
(
input clk,
input rst,
input en,
input [9:0]cont_v,
input [10:0]cont_h,
input [4:0]in_top,
input [5:0]in_top1,
input [4:0]in_top2,
output [4:0]r,
output [5:0]g,
output [4:0]b
);
reg [4:0]rgb_r;
reg [5:0]rgb_g;
reg [4:0]rgb_b;
always@(posedge clk or negedge rst)
begin
if(~rst)
begin
rgb_r<=5'b00000;
rgb_g<=6'b000000;
rgb_b<=5'b00000;
end
else if(en==1'b1)
begin
if(((11'd215<cont_h)&&(cont_h<11'd281))&&((10'd27<cont_v)&&(cont_v<10'd93)))//(((11'd614<cont_h)&&(cont_h<11'd680))&&((10'd325<cont_v)&&(cont_v<10'd391)))
begin
rgb_r<=in_top;
rgb_g<=in_top1;
rgb_b<=in_top2;
end
else
begin
rgb_r<=5'b00000;
rgb_g<=6'b000000;
rgb_b<=5'b00000;
end
end
else
begin
rgb_r<=5'b00000;
rgb_g<=6'b000000;
rgb_b<=5'b00000;
end
end
assign r=rgb_r;
assign g=rgb_g;
assign b=rgb_b;
endmodule