（9）uboot之DDR SDRAM理解 六

基于s5pv21对DDR2 SDRAM K4T1G08的初始化

ddr2_device_operation_timing_diagram_may_07-0.pdf
DS_K4T1G08_16_4QJ-B_Rev1_0-1.pdf
S5PV210_UM_REV1.1.pdf
DDR2初始化流程：（手册中有详细的寄存位说明）

自编初始化代码：

DDR2 K4T1G08	 |	s5pv210			
——————————————————————————————
Xm1 ADDR[0~15]	->	MP1_0[0~7]
				->	MP1_1[0~7]
Xm1 DATA[0~31]	->	MP1_2[0~7]
				->	MP1_3[0~7]				
				->	MP1_4[0~7]	
				->	MP1_5[0~7]	
control			->	MP1_6[0~7]
				->	MP1_7[0~7]
				->	MP1_8[0~6]				
--------------------------------------
//全局标号 可以被别的文件引用	
.globl ddrmem_init
ddrmem_init

#define APB_DMC_0_BASE		0xF0000000

#define DMC_CONCONTROL		0x00
#define DMC_MEMCONTROL		0x04
#define DMC_MEMCONFIG0		0x08
#define DMC_MEMCONFIG1		0x0C	
#define DMC_DIRECTCMD		0x10	
#define DMC_PRECHCONFIG		0x14	
#define DMC_PHYCONTROL0		0x18	
#define DMC_PHYCONTROL1		0x1C	
#define DMC_PWRDNCONFIG		0x28	
#define DMC_TIMINGAREF		0x30	
#define DMC_TIMINGROW		0x34	
#define DMC_TIMINGDATA		0x38	
#define DMC_TIMINGPOWER		0x3C
#define DMC_PHYSTATUS		0x40
		
	//step 2：set the phycontrol0.ctrl_start_point, .ctrl_inc, .ctrl_dll_on
	ldr		r0, =APB_DMC_0_BASE
	ldr		r1, =0x001010A
	str 	r1, [r0, #DMC_PHYCONTROL0]
	//step 3：set the phycontrol1.ctrl_shiftc, .ctrl_offsetc
	ldr		r1, =0x00000086
	str 	r1, [r0, #DMC_PHYCONTROL1]
	//step 4：phycontrol0 DLL start
	ldr		r1, =0x0010100B
	str 	r1, [r0, #DMC_PHYCONTROL0]
	
find_lock_val:
	//step 11:Loop until DLL is locked
	ldr r1, [r0, #DMC_PHYSTATUS] //将ro+DMC_PHYSTATUS的地址中的值读出放入r1
	and r2, r1, #0x7 //r2 = r1&0x7
	cmp r2, #0x7 //比较r2是否与0x7相等
	bne find_lock_val //如果不相等则跳转到find_lock_val,直到等到相等为止
	
	//step 12:Force Value locking 将得到的值存放在DMC_PHYCONTROL0中，以便掉电时下次使用
	and r1, #0x3fc0
	mov r2, r1, LSL #18 //r2等于r1左移18位
	orr r2, r2, #0x100000
	orr r2, r2, #0x1000
	orr r1, r2, #0x3
	str r1, [r0, #DMC_PHYCONTROL0]
	
	//step 5：concontol auto refresh off
	ldr		r1, =0x0FFF1010
	str 	r1, [r0, #DMC_CONCONTROL]
	//step 6：Memcontrol BL=4, 1 chip, DDR2 type, dynamic power down off
	ldr		r1, =0x00202400
	str 	r1, [r0, #DMC_MEMCONTROL]	
	//step 7：Memconfig0 512MB config, 8 banks, Mapping Method[12:15]0:linear
	ldr		r1, =0x20E00323
	str 	r1, [r0, #DMC_MEMCONFIG0]		
	//step 8：PrechConfig
	ldr		r1, =0xFF000000
	str 	r1, [r0, #DMC_PRECHCONFIG]
	ldr		r1, =0xFFFF00FF
	str 	r1, [r0, #DMC_PRECHCONFIG]	
	
	//step 9：TimingAref 7.8us/133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4E)
	ldr		r1, =0x0000040E
	str 	r1, [r0, #DMC_TIMINGAREF]	
	//TimingRow
	ldr		r1, =0x11122206
	str 	r1, [r0, #DMC_TIMINGROW]	
	//TimingData
	ldr		r1, =0x12240000
	str 	r1, [r0, #DMC_TIMINGDATA]		
	//TimingPower
	ldr		r1, =0x05DC0343
	str 	r1, [r0, #DMC_TIMINGPOWER]		
	
	//step 14:DirectCmd		chip0 NOP
	ldr		r1, =0x07000000
	str		r1, =[r0, #DMC_DIRECTCMD]
	//step 16:DirectCmd		chip0 PALL
	ldr		r1, =0x01000000
	str		r1, =[r0, #DMC_DIRECTCMD]	
	//step 17:DirectCmd		chip0 EMRS2
	ldr		r1, =0x00020000
	str		r1, =[r0, #DMC_DIRECTCMD]	
	//step 18:DirectCmd		chip0 EMRS3
	ldr		r1, =0x00030000
	str		r1, =[r0, #DMC_DIRECTCMD]	
	//step 19:DirectCmd		chip0 EMRS1(MEM DLL on, DQS # disable)
	ldr		r1, =0x00010000
	str		r1, =[r0, #DMC_DIRECTCMD]	
	//step 20:DirectCmd		chip0 MRS (MEM DLL reset) CL=4, BL=4
	ldr		r1, =0x00000542
	str		r1, =[r0, #DMC_DIRECTCMD]	
	//step 21:DirectCmd		chip0 PALL
	ldr		r1, =0x01000000
	str		r1, =[r0, #DMC_DIRECTCMD]		
	//step 22:DirectCmd		chip0 REFA
	ldr		r1, =0x05000000
	str		r1, =[r0, #DMC_DIRECTCMD]	
	//DirectCmd chip0 REFA
	ldr		r1, =0x05000000
	str		r1, =[r0, #DMC_DIRECTCMD]	
	//step 23:DirectCmd		chip0 MRS(MEM DLL unreset)
	ldr		r1, =0x00000442
	str		r1, =[r0, #DMC_DIRECTCMD]		
	//step 25(1):DirectCmd		chip0 EMRS1(ocd default)
	ldr		r1, =0x00010380
	str		r1, =[r0, #DMC_DIRECTCMD]	
	//step 25(2):DirectCmd		chip0 EMRS1(OCD exit)
	ldr		r1, =0x00010000
	str		r1, =[r0, #DMC_DIRECTCMD]		
	
	//step 27:ConControl auto refresh on
	ldr		r1, =0x0FF01030
	str		r1, =[r0, #DMC_DIRECTCMD]		
	//step 28:Memcontrol BL=4, 1 chip ,DDR type,dynamic self refresh
	ldr		r1, =0x00202400
	str		r1, =[r0, #DMC_DIRECTCMD]	
	
	//将lr中存放的返回地址给pc,从子程序返回
	mov		pc, lr