2021-05-07

Verilog modelsim联合仿真
一.
了解Verilog modelsim联合仿真的原理及应用
二.实验过程
1.打开quartus 打开代码页面（Verilog HDL File)将代码粘贴到页面上。
module fulladd(S,Cout,Cin,A,B);

output S,Cout;

input Cin,A,B;

wire and1,and2,and3,and4;

xor (S,Cin,A,B);

and (and1,Cin,A);

and (and2,A,B);

and (and3,Cin,B);

or (Cout,and1,and2,and3);

endmodule

module add4a(S3,S2,S1,S0,COUT,CIN,X3,X2,X1,X0,Y3,Y2,Y1,Y0);

output COUT,S3,S2,S1,S0;

input CIN, X3,X2,X1,X0,Y3,Y2,Y1,Y0;

wire c0,c1,c2;

fulladd add0(.S(S0), .Cout(c0), .Cin(CIN), .A(X0), .B(Y0));

fulladd add1(.S(S1), .Cout(c1), .Cin(c0), .A(X1), .B(Y1));

fulladd add2(.S(S2), .Cout(c2), .Cin(c1), .A(X2), .B(Y2));

fulladd add3(.S(S3), .Cout(COUT), .Cin(c2), .A(X3), .B(Y3));

endmodule

module add4(S,COUT,CIN,X,Y);//ËÄλȫ¼ÓÆ÷

output COUT;

output [3:0] S;

input CIN;

input [3:0]X,Y;

wire c0,c1,c2;

fulladd add0(.S(S[0]), .Cout(c0), .Cin(CIN), .A(X[0]), .B(Y[0]));

fulladd add1(.S(S[1]), .Cout(c1), .Cin(c0), .A(X[1]), .B(Y[1]));

fulladd add2(.S(S[2]), .Cout(c2), .Cin(c1), .A(X[2]), .B(Y[2]));

fulladd add3(.S(S[3]), .Cout(COUT), .Cin(c2), .A(X[3]), .B(Y[3]));

endmodule

module tadd4;

reg [3:0] x,y;

reg cin;

wire [3:0] s;

wire cout;

add4 myadd4(.S(s),.COUT(cout),.CIN(cin),.X(x),.Y(y));

initial

begin

cin<=0;x<=11;y<=2;

#10 cin<=0;x<=9;y<=6;

#10 cin<=0;x<=9;y<=7;

#10 cin<=1;x<=11;y<=2;

#10 cin<=1;x<=9;y<=6;

#10 cin<=1;x<=9;y<=7;

#10 $stop;

end

endmodule
2、点击左上角选择save as ,新建一个文件夹，并将代码文件命名为add4，点击保存
3、对弹出的窗口中的内容进行操作，选择modelsim，选择芯片，保存
4、找到settings选择test bench，选择刚才的fulladd文件夹，完成后点击运行，，没有问题后运行跳转到modelsim，对参数进行调整

三.实验视频

[video(video-TBO1Ah4p-1620398359205)(type-tencent)(url-https://v.qq.com/txp/iframe/player.html?vid=d3244m944u9)(image-http://puui.qpic.cn/vpic/0/d3244m944u9.png/0)(title- #腾讯视频代言人迪丽热巴#

)]

四.实验结论
学会了Verilog modelsim联合仿真的应用