2021-06-11一、实验目的 Quartus || 原理仿真 二、实验内容 移位除法器模型 三、实验代码 module div2(clk, reset, start, A, B, D, R, ok

一、实验目的
Quartus || 原理仿真
二、实验内容
移位除法器模型
三、实验代码
module div2(clk, reset, start, A, B, D, R, ok, err);
parameter n = 32;
parameter m = 16;

input clk, reset, start;
input [n-1:0] A, B;
output [n+m-1:0] D;
output [n-1:0] R;
output ok, err;

wire invalid, carry, load, run;

div_ctl UCTL(clk, reset, start, invalid, carry, load, run, err, ok);
div_datapath UDATAPATH(clk, reset, A, B, load, run, invalid, carry, D, R);

endmodule

module div_ctl(clk, reset, start, invalid, carry, load, run, err, ok);
parameter n = 32;
parameter m = 16;
parameter STATE_INIT = 3’b001;
parameter STATE_RUN = 3’b010;
parameter STATE_FINISH = 3’b100;
input clk, reset, start, invalid, carry;
output load, run, err, ok;

reg [2:0] current_state, next_state;
reg [5:0] cnt;
reg load, run, err, ok;

always @(posedg