HDLbits:Exams/review2015 fancytimer

 思路：前面状态照旧，s5用来计时clk,存储delay时间，然后counter2递减，注意这里什么时候到999，什么时候到1000就可以了！

自己做出来显示success的成就感！

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    parameter idle=0,s1=1,s2=2,s3=3,s4=4;
    parameter s5=5,waiting=6,doing=7;
    reg  [3:0] state,next_state;
    reg [1:0] counter1;  //计时四个CLK
    reg [11:0] counter2;//计时1000

    always @(posedge clk ) begin
        if(reset) state<=idle;
        else state<=next_state;
    end

    always @(*) begin
        case (state)
            idle:next_state=data?s1:idle;
            s1:next_state=data?s2:idle;
            s2:next_state=data?s2:s3;
            s3:next_state=data?s4:idle;
            s4:next_state=s5;
            s5:next_state= (counter1==2'b11)?waiting:s5;
            waiting:next_state=(count==4'b0&&counter2==12'b0)?doing:waiting;
            doing:next_state= ack?idle:doing;
        endcase
    end
    //counter1
    always @(posedge clk ) begin
        if(reset) counter1<=0;
        else counter1<= (next_state==s5)?counter1+1:0;
    end
    //counter2
    always @(posedge clk ) begin
        if(reset) counter2<=12'd1000;
        else if(counter2==12'b0) counter2<=999;
        else counter2<= (next_state==waiting)?counter2-1:12'd1000;
    end

    //输出
    always @(posedge clk ) begin
        if(reset) begin
            counting<=0;done<=0;count<=0;
        end
        else begin
            count[3:0]<=(next_state==s5||state==s5)?{count[2:0],data}:(counter2==0)?count-1:count;
            counting<=next_state==waiting;
            done<= next_state==doing;
        end
    end

endmodule