HDLBits学习：Exams/review2015 fancytimer

题目

This is the fifth component in a series of five exercises that builds a complex counter out of several smaller circuits. You may wish to do the four previous exercises first (counter, sequence recognizer FSM, FSM delay, and combined FSM).

We want to create a timer with one input that:

1. is started when a particular input pattern (1101) is detected,
2. shifts in 4 more bits to determine the duration to delay,
3. waits for the counters to finish counting, and
4. notifies the user and waits for the user to acknowledge the timer.

The serial data is available on the data input pin. When the pattern 1101 is received, the circuit must then shift in the next 4 bits, most-significant-bit first. These 4 bits determine the duration of the timer delay. I'll refer to this as the delay[3:0].

After that, the state machine asserts its counting output to indicate it is counting. The state machine must count for exactly (delay[3:0] + 1) * 1000 clock cycles. e.g., delay=0 means count 1000 cycles, and delay=5 means count 6000 cycles. Also output the current remaining time. This should be equal to delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until it is 0 for 1000 cycles. When the circuit isn't counting, the count[3:0] output is don't-care (whatever value is convenient for you to implement).

At that point, the circuit must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).

The circuit should reset into a state where it begins searching for the input sequence 1101.

Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once the 1101 and delay[3:0] have been read, the circuit no longer looks at the data input until it resumes searching after everything else is done. In this example, the circuit counts for 2000 clock cycles because the delay[3:0] value was 4'b0001. The last few cycles starts another count with delay[3:0] = 4'b1110, which will count for 15000 cycles.

AI翻译：

这是五个练习中的第五个部分，该练习从几个较小的电路中构建了一个复杂的计数器。您可能希望先进行前四个练习 （计数器,序列识别器 FSM,FSM 延迟和组合式 FSM).

我们想创建一个带有一个输入的计时器，该输入：

1. 当检测到特定输入模式 （1101） 时启动，
2. 再移动 4 个位以确定延迟的持续时间，
3. 等待计数器完成计数，然后
4. 通知用户并等待用户确认计时器。

串行数据在数据输入引脚上可用。当接收到模式 1101 时，电路必须在接下来的 4 位中移位，首先是最高有效位。这 4 位决定了定时器延迟的持续时间。我将此称为延迟[3：0]。

之后，状态机断言其计数输出以指示它正在计数。状态机必须精确计数 （delay[3：0] + 1） * 1000 个时钟周期。例如，delay=0 表示计数 1000 个周期，delay=5 表示计数 6000 个周期。还输出当前剩余时间。这应该等于 1000 个周期的延迟，然后等于 1000 个周期的延迟 1，依此类推，直到 1000 个周期为 0。当电路不计数时，count[3：0] 输出为 dont-care（无论您方便实现任何值）。

此时，电路必须断言完成以通知用户计时器已超时，并等待输入确认为1，然后再被复位以寻找下一次出现的启动序列（1101）。

电路应复位到开始搜索输入序列1101的状态。

下面是预期输入和输出的示例。“x”状态可能读起来有点令人困惑。它们表明FSM不应关心该周期中的特定输入信号。例如，一旦读取了 1101 和延迟[3：0]，电路就不再查看数据输入，直到在完成其他所有操作后恢复搜索。在此示例中，电路计数 2000 个时钟周期，因为 delay[3：0] 值为 4'b0001。最后几个周期以 delay[3：0] = 4'b1110 开始另一个计数，这将计算 15000 个周期。

分析：本题思路和上一次大致一样，唯一区别在于多一个计数器来拉高done_counting使，状态转换到Wait状态

状态转换图参考网站提示图如下:

实现代码如下：

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output reg [3:0] count,
    output counting,
    output done,
    input ack );

parameter S      = 4'd0;
parameter S1     = 4'd1;
parameter S11    = 4'd2;
parameter S110   = 4'd3;
parameter B0     = 4'd4;
parameter B1     = 4'd5;
parameter B2     = 4'd6;
parameter B3     = 4'd7;
parameter Count  = 4'd8;
parameter Wait   = 4'd9;

reg [3:0] state     ;
reg [3:0] next_state;
reg [15:0] cnt_1000;
reg done_counting;
//状态转换
always @(*) begin
    case(state)
S    :next_state=data ?S1 :S              ;
S1   :next_state=data ?S11:S              ;
S11  :next_state=data ?S11:S110           ;
S110 :next_state=data ?B0 :S              ;
B0   :next_state=B1                       ;
B1   :next_state=B2                       ;
B2   :next_state=B3                       ;
B3   :next_state=Count                    ;
Count:next_state=done_counting?Wait:Count ;
Wait :next_state=ack?S:Wait               ;
    default:;
    endcase
end
//输出计数
always @(posedge clk) begin
    case(state)
B0:count[3]=data ;//获取数据
B1:count[2]=data ;
B2:count[1]=data ;
B3:count[0]=data ;
default:;
    endcase
if(state==Count)begin
    if(count>=0)begin
        done_counting<=0;
        if(cnt_1000==16'd998&count==0)//在此时捕获
        done_counting<=1;
        else if(cnt_1000==16'd999)
        count<=count-4'd1;
    end
end
end
//状态转换
always @(posedge clk) begin
if(reset)
state<=S;
else
state<=next_state;    
end
//1000进制计数器
always @(posedge clk) begin
    if(state==B3)
    cnt_1000<=16'd0;
    else if(cnt_1000<16'd999)
    cnt_1000<=cnt_1000+16'd1;
    else
    cnt_1000<=16'd0;  
end
//输出
assign counting  =  (state==Count)                                 ;
assign done      =  (state==Wait)                                  ;
endmodule