简介
基于DE2-115 FPGA开发板与软件quartus开发
VGA驱动显示器用的是扫描的方式，一般是逐行扫描。
逐行扫描是扫描从屏幕左上角一点开始，从左像右逐点扫描，每扫描完一行,电子束回到屏幕的左边下一行的起始位置，在这期间，CRT对电子束进行消隐，每行结束时，用行同步信号进行同步；
当扫描完所有的行，形成一帧后，用场同步信号进行场同步，并使扫描回到屏幕左上方，同时进行场消隐,开始下一帧。
一、屏幕上显示彩色条纹
1.新建项目
- 打开quartus新建项目
file->new project wizard…
- 新建文件夹并选择
- 填写项目名称，一路next，选择开发板后next
- 配置仿真工具后finish
2.利用Verilog HDL语言设计模块
-
新建Verilog HDL文本文件
-
创建pll的ip核，view打开ip catalog
-
出现下图，输入pll，点击ALPLL
-
点击OK
-
时钟频率选择50MHZ，选择正常模式后next，如下图
-
取消勾选输出使能
-
.c0默认输出50M即可,c1分频到25M,如需其他时钟频率可以自己进行设置
-
勾选如下选项后finish
3.源代码
- rgb信号产生模块vga_control
// `define Vga_800_600
`include "vga_param.v"
module vga_control(
input wire clk ,//vga pix clk 800*525*60 25.2MHZ
input wire rst_n ,//reset
input wire [23:0] data_disp,//
output reg [10:0] h_addr ,//数据有效显示区域行地址
output reg [10:0] v_addr ,//数据有效显示区域场地址
output reg hsync ,//
output reg vsync ,//
output reg [7:0] vga_r ,//red
output reg [7:0] vga_g ,//green
output reg [7:0] vga_b ,//blue
output reg vga_blk ,//消隐信号
output wire vga_clk
);
//
parameter H_SYNC_STA = 1 ;
parameter H_SYNC_END = `H_Sync_Time ;
parameter H_Data_STA = `H_Right_Border + `H_Front_Porch + `H_Sync_Time ;
parameter H_Data_STO = `H_Right_Border + `H_Front_Porch + `H_Sync_Time + `H_Data_Time;
parameter V_SYNC_STA = 1 ;
parameter V_SYNC_END = `V_Sync_Time ;
parameter V_Data_STA = `V_Bottom_Borde + `V_Front_Porch + `V_Sync_Time ;
parameter V_Data_STO = `V_Bottom_Borde + `V_Front_Porch + `V_Sync_Time + `V_Data_Time;
//参数定义
reg [11:0] cnt_h_addr;//行地址计数器
wire add_h_addr;//
wire end_h_addr;//
reg [11:0] cnt_v_addr;//场地址计数器
wire add_v_addr;//
wire end_v_addr;//
//cnt_h_addr 0-799
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt_h_addr <= 12'b0;
end
else if(add_h_addr)begin
if(end_h_addr)begin
cnt_h_addr <= 12'b0;
end
else begin
cnt_h_addr <= cnt_h_addr + 12'b1;
end
end
else begin
cnt_h_addr <= cnt_h_addr;
end
end
assign add_h_addr = 1'b1;
assign end_h_addr = add_h_addr && cnt_h_addr >= `H_Total_Time - 1;
//cnt_v_addr 0-524
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt_v_addr <= 12'b0;
end
else if(add_v_addr)begin
if(end_v_addr)begin
cnt_v_addr <= 12'b0;
end
else begin
cnt_v_addr <= cnt_v_addr + 12'b1;
end
end
else begin
cnt_v_addr <= cnt_v_addr;
end
end
assign add_v_addr = end_h_addr;
assign end_v_addr = add_v_addr && cnt_v_addr >= `V_Total_Time - 1;
//行同步信号
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
hsync <= 1'b1;
end
else if(cnt_h_addr == H_SYNC_STA - 1)begin
hsync <= 1'b0;
end
else if(cnt_h_addr == H_SYNC_END - 1)begin
hsync <= 1'b1;
end
else begin
hsync <= hsync;
end
end
//场同步信号
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
vsync <= 1'b1;
end
else if(cnt_v_addr == V_SYNC_STA - 1)begin
vsync <= 1'b0;
end
else if(cnt_v_addr == V_SYNC_END - 1)begin
vsync <= 1'b1;
end
else begin
vsync <= vsync;
end
end
assign vga_clk = ~clk;
//h_addr 数据有效显示区域 1-640
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
h_addr <= 11'b0;
end
else if((cnt_h_addr >= H_Data_STA - 1) && (cnt_h_addr <= H_Data_STO - 1))begin
h_addr <= cnt_h_addr - (H_Data_STA - 1);//0-640
end
else begin
h_addr <= 11'b0;
end
end
//v_addr 数据有效显示区域 1-480
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
v_addr <= 11'b0;
end
else if((cnt_v_addr >= V_Data_STA - 1) && (cnt_v_addr <= V_Data_STO - 1))begin
v_addr <= cnt_v_addr - (V_Data_STA - 1);//0-480
end
else begin
v_addr <= 11'b0;
end
end
//显示
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
vga_r <= 8'b0000_0000;
vga_g <= 8'b0000_0000;
vga_b <= 8'b0000_0000;
vga_blk <= 1'b0;
end
else if((cnt_h_addr >= H_Data_STA - 1) && (cnt_h_addr <= H_Data_STO - 1)&&
(cnt_v_addr >= V_Data_STA - 1) && (cnt_v_addr <= V_Data_STO - 1))begin
vga_r <= data_disp[23:16];//data_disp[23-:8]
vga_g <= data_disp[15:8] ;//data_disp[15-:8]
vga_b <= data_disp[7:0] ;//data_disp[7-:8]
vga_blk <= 1'b1;
end
else begin
vga_r <= 8'b0000_0000;
vga_g <= 8'b0000_0000;
vga_b <= 8'b0000_0000;
vga_blk <= 1'b0;
end
end
endmodule
- rgb输出模块data_gen
module data_gen(
input wire clk ,//vga pix clk 640*800*60 25.2MHZ
input wire rst_n ,//reset
input wire [10:0] h_addr ,//数据有效显示区域行地址
input wire [10:0] v_addr ,//数据有效显示区域场地址
output reg [23:0] data_disp //
);
parameter H_vga = 640,//屏幕宽度
V_vga = 480,//屏幕高度
X_vga = 288,//字符宽度
Y_vga = 32 ;//字符高度
//
parameter BLACK = 24'h000000,
RED = 24'hFF0000,
GREEN = 24'h00FF00,
BLUE = 24'h0000FF,
YELLOW = 24'hFFFF00,
SKY_BLUE= 24'h00FFFF,
PURPLE = 24'hFF00FF,
GRAY = 24'hC0C0C0,
WHITE = 24'hFFFFFF;
//
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_disp <= GRAY;
end
else begin
case(h_addr)
0 : data_disp <=BLACK ;
80 : data_disp <=RED ;
160: data_disp <=GREEN ;
240: data_disp <=BLUE ;
320: data_disp <=YELLOW ;
400: data_disp <=SKY_BLUE ;
480: data_disp <=PURPLE ;
560: data_disp <=GRAY ;
default :data_disp <= data_disp ;
endcase
end
end
endmodule
- 时钟产生定义模块vga_param
`define Vga_480_272
`define Vga_640_480
`define Vga_800_480
`define Vga_800_600
`define Vga_1024_600
`define Vga_1024_768
`define Vga_1280_720
`define Vga_1920_1080
//`ifdef Vga_800_600
// `define H_Right_Border 0
// `define H_Front_Porch 40
// `define H_Sync_Time 128
// `define H_back_Porch 88
// `define H_Left_Border 0
// `define H_Data_Time 800
// `define H_Total_Time 1056
//
// `define V_Bottom_Borde 0
// `define V_Front_Porch 1
// `define V_Sync_Time 4
// `define V_Back_Porch 23
// `define V_ToP_Border 0
// `define V_Data_Time 600
// `define V_Total_Time 628
`ifdef Vga_640_480
`define H_Right_Border 8
`define H_Front_Porch 8
`define H_Sync_Time 96
`define H_back_Porch 40
`define H_Left_Border 8
`define H_Data_Time 640
`define H_Total_Time 800
`define V_Bottom_Borde 8
`define V_Front_Porch 2
`define V_Sync_Time 2
`define V_Back_Porch 25
`define V_ToP_Border 8
`define V_Data_Time 480
`define V_Total_Time 525
`elsif Vga_480_272
`define H_Right_Border 0
`define H_Front_Porch 2
`define H_Sync_Time 41
`define H_back_Porch 2
`define H_Left_Border 0
`define H_Data_Time 480
`define H_Total_Time 525
`define V_Bottom_Borde 0
`define V_Front_Porch 2
`define V_Sync_Time 10
`define V_Back_Porch 2
`define V_ToP_Border 0
`define V_Data_Time 272
`define V_Total_Time 286
`elsif Vga_800_480
`define H_Right_Border 0
`define H_Front_Porch 40
`define H_Sync_Time 128
`define H_back_Porch 88
`define H_Left_Border 0
`define H_Data_Time 800
`define H_Total_Time 1056
`define V_Bottom_Borde 8
`define V_Front_Porch 2
`define V_Sync_Time 2
`define V_Back_Porch 25
`define V_ToP_Border 8
`define V_Data_Time 480
`define V_Total_Time 525
`elsif Vga_800_600
`define H_Right_Border 0
`define H_Front_Porch 40
`define H_Sync_Time 128
`define H_back_Porch 88
`define H_Left_Border 0
`define H_Data_Time 800
`define H_Total_Time 1056
`define V_Bottom_Borde 0
`define V_Front_Porch 1
`define V_Sync_Time 4
`define V_Back_Porch 23
`define V_ToP_Border 0
`define V_Data_Time 600
`define V_Total_Time 628
`elsif Vga_1024_600
`define H_Rigth_Borde 0
`define H_Front_Porch 24
`define H_Sync_Time 136
`define H_Back_Porch 160
`define H_Left_Border 0
`define H_Data_Time 1024
`define H_Total_Time 1344
`define V_Bottom_Borde 0
`define V_Front_Porch 1
`define V_Sync_Time 4
`define V_Back_Porch 23
`define V_ToP_Border 0
`define V_Data_Time 600
`define V_Total_Time 628
`elsif Vga_1024_768
`define H_Rigth_Borde 0
`define H_Front_Porch 24
`define H_Sync_Time 136
`define H_Back_Porch 160
`define H_Left_Border 0
`define H_Data_Time 1024
`define H_Total_Time 1344
`define V_Bottom_Borde 0
`define V_Front_Porch 3
`define V_Sync_Time 6
`define V_Back_Porch 29
`define V_ToP_Border 0
`define V_Data_Time 768
`define V_Total_Time 806
`elsif Vga_1280_720
`define H_Rigth_Borde 0
`define H_Front_Porch 110
`define H_Sync_Time 40
`define H_Back_Porch 220
`define H_Left_Border 0
`define H_Data_Time 1280
`define H_Total_Time 1650
`define V_Bottom_Borde 0
`define V_Front_Porch 5
`define V_Sync_Time 5
`define V_Back_Porch 20
`define V_ToP_Border 0
`define V_Data_Time 720
`define V_Total_Time 750
`elsif Vga_1920_1080
`define H_Right_Border 0
`define H_Front_Porch 88
`define H_Sync_Time 44
`define H_back_Porch 148
`define H_Left_Border 0
`define H_Data_Time 1920
`define H_Total_Time 2200
`define V_Bottom_Borde 0
`define V_Front_Porch 4
`define V_Sync_Time 5
`define V_Back_Porch 36
`define V_ToP_Border 0
`define V_Data_Time 1080
`define V_Total_Time 1125
`endif
- 顶层模块vga_top
module vga_top(
input wire clk ,//vga pix clk 640*800*60 25.2MHZ
input wire rst_n , //reset
output wire [7:0] vga_r ,
output wire [7:0] vga_g ,
output wire [7:0] vga_b ,
output wire vga_blk ,
output wire vga_clk ,
output wire vsync ,
output wire hsync
);
wire [23:0] data_disp;
wire [10:0] h_addr;
wire [10:0] v_addr;
wire vga_25;
wire vga_40;
wire locked;
pll pll_inst (
.areset ( ~rst_n ),
.inclk0 ( clk ),
.c0 ( vga_25 ),
.c1 ( vga_40 ),
.locked ( locked )
);
vga_control u_vga_control(
.clk (vga_25 ),//vga pix clk 640*800*60 25.2MHZ
.rst_n (rst_n ),//reset
.data_disp (data_disp),//
.h_addr (h_addr ),//数据有效显示区域行地址
.v_addr (v_addr ),//数据有效显示区域场地址
.hsync (hsync ),//
.vsync (vsync ),//
.vga_r (vga_r ),//red
.vga_g (vga_g ),//green
.vga_b (vga_b ),//blue
.vga_blk (vga_blk ),//消隐信号
.vga_clk (vga_clk )
);
data_gen u_data_gen(
.clk (vga_25 ),//vga pix clk 640*800*60 25.2MHZ
.rst_n (rst_n ),//reset
.h_addr (h_addr ),//数据有效显示区域行地址
.v_addr (v_addr ),//数据有效显示区域场地址
.data_disp (data_disp) //
);
endmodule
- 管脚配置
4.实验结果
二、显示自定义的字符
1.创建项目
- 步骤基本上不变，按之前步骤做即可
- 重点是提取字模，需要字模提取工具
- 配置如下，点击确定：
- 生成
2.源代码
module VGA_test(
OSC_50, //原CLK2_50时钟信号
VGA_CLK, //VGA自时钟
VGA_HS, //行同步信号
VGA_VS, //场同步信号
VGA_BLANK, //复合空白信号控制信号 当BLANK为低电平时模拟视频输出消隐电平，此时从R9~R0,G9~G0,B9~B0输入的所有数据被忽略
VGA_SYNC, //符合同步控制信号 行时序和场时序都要产生同步脉冲
VGA_R, //VGA绿色
VGA_B, //VGA蓝色
VGA_G); //VGA绿色
input OSC_50; //外部时钟信号CLK2_50
output VGA_CLK,VGA_HS,VGA_VS,VGA_BLANK,VGA_SYNC;
output [7:0] VGA_R,VGA_B,VGA_G;
parameter H_FRONT = 16; //行同步前沿信号周期长
parameter H_SYNC = 96; //行同步信号周期长
parameter H_BACK = 48; //行同步后沿信号周期长
parameter H_ACT = 640; //行显示周期长
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK; //行空白信号总周期长
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT; //行总周期长耗时
parameter V_FRONT = 11; //场同步前沿信号周期长
parameter V_SYNC = 2; //场同步信号周期长
parameter V_BACK = 31; //场同步后沿信号周期长
parameter V_ACT = 480; //场显示周期长
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK; //场空白信号总周期长
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT; //场总周期长耗时
reg [10:0] H_Cont; //行周期计数器
reg [10:0] V_Cont; //场周期计数器
wire [7:0] VGA_R; //VGA红色控制线
wire [7:0] VGA_G; //VGA绿色控制线
wire [7:0] VGA_B; //VGA蓝色控制线
reg VGA_HS;
reg VGA_VS;
reg [10:0] X; //当前行第几个像素点
reg [10:0] Y; //当前场第几行
reg CLK_25;
always@(posedge OSC_50)
begin
CLK_25=~CLK_25; //时钟
end
assign VGA_SYNC = 1'b0; //同步信号低电平
assign VGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK)); //当行计数器小于行空白总长或场计数器小于场空白总长时，空白信号低电平
assign VGA_CLK = ~CLK_to_DAC; //VGA时钟等于CLK_25取反
assign CLK_to_DAC = CLK_25;
always@(posedge CLK_to_DAC)
begin
if(H_Cont<H_TOTAL) //如果行计数器小于行总时长
H_Cont<=H_Cont+1'b1; //行计数器+1
else H_Cont<=0; //否则行计数器清零
if(H_Cont==H_FRONT-1) //如果行计数器等于行前沿空白时间-1
VGA_HS<=1'b0; //行同步信号置0
if(H_Cont==H_FRONT+H_SYNC-1) //如果行计数器等于行前沿+行同步-1
VGA_HS<=1'b1; //行同步信号置1
if(H_Cont>=H_BLANK) //如果行计数器大于等于行空白总时长
X<=H_Cont-H_BLANK; //X等于行计数器-行空白总时长 （X为当前行第几个像素点）
else X<=0; //否则X为0
end
always@(posedge VGA_HS)
begin
if(V_Cont<V_TOTAL) //如果场计数器小于行总时长
V_Cont<=V_Cont+1'b1; //场计数器+1
else V_Cont<=0; //否则场计数器清零
if(V_Cont==V_FRONT-1) //如果场计数器等于场前沿空白时间-1
VGA_VS<=1'b0; //场同步信号置0
if(V_Cont==V_FRONT+V_SYNC-1) //如果场计数器等于行前沿+场同步-1
VGA_VS<=1'b1; //场同步信号置1
if(V_Cont>=V_BLANK) //如果场计数器大于等于场空白总时长
Y<=V_Cont-V_BLANK; //Y等于场计数器-场空白总时长 （Y为当前场第几行）
else Y<=0; //否则Y为0
end
reg valid_yr;
always@(posedge CLK_to_DAC)
if(V_Cont == 10'd32) //场计数器=32时
valid_yr<=1'b1; //行输入激活
else if(V_Cont==10'd512) //场计数器=512时
valid_yr<=1'b0; //行输入冻结
wire valid_y=valid_yr; //连线
reg valid_r;
always@(posedge CLK_to_DAC)
if((H_Cont == 10'd32)&&valid_y) //行计数器=32时
valid_r<=1'b1; //像素输入激活
else if((H_Cont==10'd512)&&valid_y) //行计数器=512时
valid_r<=1'b0; //像素输入冻结
wire valid = valid_r; //连线
wire[10:0] x_dis; //像素显示控制信号
wire[10:0] y_dis; //行显示控制信号
assign x_dis=X; //连线X
assign y_dis=Y; //连线Y
parameter //点阵字模：每一行char_lineXX是显示的一行，共272列
char_line00=288'h00000000_00000000_00000000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000, //第1行
char_line01=288'h00000000_00000000_00000000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000, //第2行
char_line02=288'h00802000_00060000_00020000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000, //第3行
char_line03=288'h01C03800_00030000_00018000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000, //第4行
char_line04=288'h01803000_00018000_0001C000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000, //第5行
char_line05=288'h03806800_0001C000_0000C000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000, //第6行
char_line06=288'h0300E400_04008010_00008030_01E0_07C0_0080_07C0_03C0_1FFC_0000_01E0_03C0_0000_0000_0FFC, //第7行
char_line07=288'h0600C600_07FFFFF8_07FFFFF8_0618_1860_0180_1820_0620_1FFC_03C0_0618_0620_07E0_07E0_0FFC, //第8行
char_line08=288'h0C018300_0C000038_04000030_0C18_3030_1F80_3010_0C30_1008_0620_0C18_0C30_0838_0838_1000, //第9行
char_line09=288'h08E30180_0C000020_0C000060_0818_3018_0180_3018_1818_3010_0C30_0818_1818_1018_1018_1000, //第10行
char_line0a=288'h10E200E0_1C030040_0C000040_1800_3018_0180_6008_1818_2010_1818_1800_1818_200C_200C_1000, //第11行
char_line0b=288'h21C40078_18038000_0C000000_1000_3018_0180_600C_1808_2020_1818_1000_1808_200C_200C_1000, //第12行
char_line0c=288'h018801BC_00030000_00000300_1000_0018_0180_600C_300C_0020_1808_1000_300C_300C_300C_1000, //第13行
char_line0d=288'h0317FFC0_00030020_01FFFF80_3000_0018_0180_600C_300C_0040_300C_3000_300C_300C_300C_1000, //第14行
char_line0e=288'h03201000_00060070_00018000_33E0_0030_0180_600C_300C_0040_300C_33E0_300C_000C_000C_13E0, //第15行
char_line0f=288'h07401000_1FFFFFF8_00018000_3630_0060_0180_600C_300C_0040_300C_3630_300C_0018_0018_1430, //第16行
char_line10=288'h0F001000_00060000_00018000_3818_03C0_0180_701C_300C_0080_300C_3818_300C_0018_0018_1818, //第17行
char_line11=288'h0B001030_000C0000_00018010_3808_0070_0180_302C_300C_0080_300C_3808_300C_0030_0030_1008, //第18行
char_line12=288'h131FFFF8_000C2000_00018038_300C_0018_0180_186C_300C_0100_300C_300C_300C_0060_0060_000C, //第19行
char_line13=288'h23001000_00187000_3FFFFFFC_300C_0008_0180_0F8C_300C_0100_300C_300C_300C_00C0_00C0_000C, //第20行
char_line14=288'h43001000_00186000_00018000_300C_000C_0180_000C_300C_0100_300C_300C_300C_0180_0180_000C, //第21行
char_line15=288'h03021000_0030C000_00018000_300C_000C_0180_0018_300C_0100_300C_300C_300C_0300_0300_000C, //第22行
char_line16=288'h03071100_0060C000_00018000_300C_300C_0180_0018_1808_0300_300C_300C_1808_0200_0200_300C, //第23行
char_line17=288'h030610C0_00618200_00018000_180C_300C_0180_0010_1818_0300_1808_180C_1818_0404_0404_300C, //第24行
char_line18=288'h030C1060_00C30100_00018000_1808_3008_0180_3030_1818_0300_1818_1808_1818_0804_0804_2018, //第25行
char_line19=288'h03081030_01820180_00018000_0C18_3018_0180_3060_0C30_0300_1818_0C18_0C30_1004_1004_2018, //第26行
char_line1a=288'h03101038_020400C0_00018000_0E30_1830_03C0_30C0_0620_0300_0C30_0E30_0620_200C_200C_1830, //第27行
char_line1b=288'h03201018_0C080060_00018000_03E0_07C0_1FF8_0F80_03C0_0300_0620_03E0_03C0_3FF8_3FF8_07C0, //第28行
char_line1c=288'h0341F018_103FFFF0_003F8000_0000_0000_0000_0000_0000_0000_03C0_0000_0000_3FF8_3FF8_0000, //第29行
char_line1d=288'h03007000_601E0030_00070000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000, //第30行
char_line1e=288'h02000000_00100020_00020000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000, //第31行
char_line1f=288'h00000000_00000000_00000000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; //第32行
reg[8:0] char_bit;
always@(posedge CLK_to_DAC)
if(X==10'd144)char_bit<=9'd288; //当显示到144像素时准备开始输出图像数据
else if(X>10'd144&&X<10'd432) //左边距屏幕144像素到416像素时 432=144+272（图像宽度）
char_bit<=char_bit-1'b1; //倒着输出图像信息
reg[29:0] vga_rgb; //定义颜色缓存
always@(posedge CLK_to_DAC)
if(X>10'd144&&X<10'd432) //X控制图像的横向显示边界：左边距屏幕左边144像素 右边界距屏幕左边界416像素
begin cas/e(Y) //Y控制图像的纵向显示边界：从距离屏幕顶部160像素开始显示第一行数据
10'11:
if(char_line00[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000; //如果该行有数据 则颜色为红色
else vga_rgb<=30'b0000000000_0000000000_0000000000; //否则为黑色
10'd162:
if(char_line01[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd163:
if(char_line02[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd164:
if(char_line03[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd165:
if(char_line04[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd166:
if(char_line05[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd167:
if(char_line06[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd168:
if(char_line07[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd169:
if(char_line08[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd170:
if(char_line09[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd171:
if(char_line0a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd172:
if(char_line0b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd173:
if(char_line0c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd174:
if(char_line0d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd175:
if(char_line0e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd176:
if(char_line0f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd177:
if(char_line10[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd178:
if(char_line11[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd179:
if(char_line12[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd180:
if(char_line13[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd181:
if(char_line14[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd182:
if(char_line15[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd183:
if(char_line16[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd184:
if(char_line17[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd185:
if(char_line18[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd186:
if(char_line19[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd187:
if(char_line1a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd188:
if(char_line1b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd189:
if(char_line1c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd190:
if(char_line1d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd191:
if(char_line1e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd192:
if(char_line1f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
default:vga_rgb<=30'h0000000000; //默认颜色黑色
endcase
end
else vga_rgb<=30'h000000000; //否则黑色
assign VGA_R=vga_rgb[23:16];
assign VGA_G=vga_rgb[15:8];
assign VGA_B=vga_rgb[7:0];
endmodule
- 引脚配置
3.实验结果
三、总结
做了彩条、字符显示，都完成了，就是内容比较多，理解了原理代码也比较好懂，信号的变化和输入输出一定要仔细分析。
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