C语言思维
always @(posedge clk or posedge reset)
if (reset == 1'b1)
begin
rdddr_total_cnt <= 7'b0000001;
rdddr_src_out_delay <= {4{1'b0}};
rdddr_src_rd_done <= 1'b0;
end
else
begin
rdddr_src_out_delay <= rdddr_src_out[3:0];
rdddr_src_rd_done <= rdddr_src_rd_req;
if (ddr_rdvalid == 1'b1)
begin
rdddr_total_cnt <= rdddr_total_cnt + 1;
if (rdddr_total_cnt == rdddr_src_out[10:4])
rdddr_total_cnt <= 7'b0000001;
end
end
硬件(Verilog)思维
always @(posedge clk or posedge reset)
if (reset) rdddr_total_cnt <= 1;
else if (rdddr_total_cnt == rdddr_src_out[10:4]) rdddr_total_cnt <= 1;
else if (ddr_rdvalid == 1'b1) rdddr_total_cnt <= rdddr_total_cnt + 1;
always @(posedge clk or posedge reset)
if (reset) rdddr_src_out_delay <= 4'b0;
else rdddr_src_out_delay <= rdddr_src_out[3:0];
always @(posedge clk or posedge reset)
if (reset) rdddr_src_rd_done <= 1'b0;
else rdddr_src_rd_done <= rdddr_src_rd_req;
我认为前者对人更友好,逻辑,一目了然。后者对硬件更友好,这种风格硬件时序会更好。
欢迎讨论!