The SR flip flop is a one-bit memory device with 2 inputs. The S (set) input causes the output Q to be set to 1. The R (reset) input causes the output Q to be 0. S=1 and R =1 is invalid. The SR flip-flop can be constructed with 2 NOR gates or 2 AND gates.
SR flip-flop with 2 NOR gates
| S | R | Q | Q' |
| Initial -> Final | Initial -> final | ||
| 0 | 0 | 0 -> 0 1 -> 1 | 1 -> 1 0 -> 0 |
| 1 | 0 | 0 -> 1 1 -> 1 | 1 -> 0 0 -> 0 |
| 0 | 1 | 0 -> 0 1 -> 0 | 1 -> 1 0 -> 1 |
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SR flip-flop with 2 NAND gates
| S | R | Q | Q' |
| Initial -> Final | Initial -> final | ||
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| 1 | 0 | 0 -> 0 1 -> 0 | 1 -> 1 0 -> 1 |
| 0 | 1 | 0 -> 1 1 -> 1 | 1 -> 0 0 -> 0 |
| 1 | 1 | 0 -> 0 1 -> 1 | 1 -> 1 0 -> 0 |
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