XAPP585代码解读——(1)DDR_TX

zidan1412

已于 2024-03-01 00:35:25 修改

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分类专栏： XILINX_XAPP 文章标签： fpga

于 2024-02-28 21:59:29 首次发布

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parameter integer     D = 5 ;               
// Set the number of outputs per channel to be 5 in this example

parameter [D-1:0] TX_SWAP_MASK = 16'h0000 ;     
// pinswap mask for output bits (0 = no swap (default), 1 = swap). 
//Allows outputs to be connected the 'wrong way round' to ease PCB routing.

genvar i ;
genvar j ;

    generate
    for (i = 0 ; i <= (D-1) ; i = i+1) begin : loop0
        for (j = 0 ; j <= 13 ; j = j+1) begin : loop1
            if (DATA_FORMAT == "PER_CLOCK") begin
                assign mdataina[14*i+j] = dataint[D*j+i] ^ TX_SWAP_MASK[i] ;
            end
            else begin
                if (j < 7) begin
                    assign mdataina[14*i+j] = dataint[(7*i)+j] ^ TX_SWAP_MASK[i] ;
                end
                else begin
                    assign mdataina[14*i+j] = dataint[(7*i)+j-7+D*7] ^ TX_SWAP_MASK[i];
                end
            end
        end
    end
    endgenerate

// Timing generator
always @ (posedge txclk_div) begin
if (reset == 1'b1) begin
    clockb2 <= 1'b0 ;
end
else begin
    clockb2 <= ~clockb2 ;
end
end
always @ (posedge pixel_clk) begin
    clockb2d_a <= clockb2 ;
    clockb2d_b <= clockb2d_a ;
    sync <= clockb2d_a ^ clockb2d_b ;
    if (sync == 1'b1) begin
        holdreg <= datain ;
    end
end
assign dataint = {datain, holdreg} ;

OSERDESE2 #(
    .DATA_WIDTH         (14),           // SERDES word width
    .TRISTATE_WIDTH         (1), 
    .DATA_RATE_OQ       ("DDR"),        // <SDR>, DDR
    .DATA_RATE_TQ       ("SDR"),        // <SDR>, DDR
    .SERDES_MODE        ("MASTER"))         // <DEFAULT>, MASTER, SLAVE
oserdes_m (
    .OQ             (tx_data_out[i]),
    .OCE            (1'b1),
    .CLK            (txclk),
    .RST            (reset_intr),
    .CLKDIV         (txclk_div),
    .D8             (mdataina[(14*i)+7]),
    .D7             (mdataina[(14*i)+6]),
    .D6             (mdataina[(14*i)+5]),
    .D5             (mdataina[(14*i)+4]),
    .D4             (mdataina[(14*i)+3]),
    .D3             (mdataina[(14*i)+2]),
    .D2             (mdataina[(14*i)+1]),
    .D1             (mdataina[(14*i)+0]),
    .TQ             (),
    .T1             (1'b0),
    .T2             (1'b0),
    .T3             (1'b0),
    .T4             (1'b0),
    .TCE            (1'b1),
    .TBYTEIN        (1'b0),
    .TBYTEOUT       (),
    .OFB            (),
    .TFB            (),
    .SHIFTOUT1      (),         
    .SHIFTOUT2      (),         
    .SHIFTIN1       (cascade_di[i]),    
    .SHIFTIN2       (cascade_ti[i])) ;  

OSERDESE2 #(
    .DATA_WIDTH         (14),           // SERDES word width.
    .TRISTATE_WIDTH         (1), 
    .DATA_RATE_OQ       ("DDR"),        // <SDR>, DDR
    .DATA_RATE_TQ       ("SDR"),        // <SDR>, DDR
    .SERDES_MODE        ("SLAVE"))      // <DEFAULT>, MASTER, SLAVE
oserdes_s (
    .OQ             (),
    .OCE            (1'b1),
    .CLK            (txclk),
    .RST            (reset_intr),
    .CLKDIV         (txclk_div),
    .D8             (mdataina[(14*i)+13]),
    .D7             (mdataina[(14*i)+12]),
    .D6             (mdataina[(14*i)+11]),
    .D5             (mdataina[(14*i)+10]),
    .D4             (mdataina[(14*i)+9]),
    .D3             (mdataina[(14*i)+8]),
    .D2             (1'b0),
    .D1             (1'b0),
    .TQ             (),
    .T1             (1'b0),
    .T2             (1'b0),
    .T3             (1'b0),
    .T4             (1'b0),
    .TCE            (1'b1),
    .TBYTEIN        (1'b0),
    .TBYTEOUT       (),
    .OFB            (),
    .TFB            (),
    .SHIFTOUT1      (cascade_di[i]),    
    .SHIFTOUT2      (cascade_ti[i]),    
    .SHIFTIN1       (1'b0),         
    .SHIFTIN2       (1'b0)) ;           
end
endgenerate