VHDL语言描述的例题

 
半整数分拼

想出了一个半整数分频的VHDL语言描述
其实很多问题只要你耐心，也是比较容易的
写出来与大家共享，共同讨论，半整数分频当然还有其他的方法
我认为这种看起来蛮简单的
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityabcis
port(clk:instd_logic;
dout:outstd_logic);
endabc;
architecturexofabcis
signalp,q:std_logic_vector(2downto0);
begin
process(clk)
begin
if(clk'eventandclk='1')then
ifp="100"thenp<="000";elsep<=p+1;
endif;endif;endprocess;
process(clk)
begin
if(clk'eventandclk='0')then
ifq="100"thenq<="000";elseq<=q+1;
endif;endif;endprocess;
dout<='1'whenp="000"orq="010"else'0';endx;
在MAXPLUS2里编译通过
仿真图也是正确的
这个是2。5分频，如果是其他半整数分频修改参数即可

loading...
 

2006-3-25
任意奇数次分频的VHDL程序

任意奇数次分频的VHDL程序
kuerle发表于2006-1-2319:53:00
LIBRARYIEEE;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_1164.ALL;

ENTITYDEV3IS
GENERIC(N:INTEGER:=3)
PORT(CLK,CLR:INSTD_LOGIC;
CLKOUT:OUTSTD_LOGIC);
ENDENTITY;

ARCHITECTURERTLOFDEV3IS
SIGNALCOUNTER1:INTEGERRANGE0TON-1;
SIGNALCOUNTER2:INTEGERRANGE0TON-1;
SIGNALCLK_REG,CLK_REG1:STD_LOGIC;

BEGIN

PROCESS(CLR,CLK)
BEGIN

IFCLR='1'THEN
COUNTER1<=0;
CLK_REG<='0';
ELSIFCLK'EVENTANDCLK='1'THEN
IFCOUNTER1=N-1THEN
COUNTER1<=0;
CLK_REG<=NOTCLK_REG;
ELSIFCOUNTER1=(N-1)/2THEN
COUNTER1<=COUNTER1+1;
CLK_REG<=NOTCLK_REG;
ELSE
COUNTER1<=COUNTER1+1;
ENDIF;
ENDIF;
ENDPROCESS;

PROCESS(CLR,CLK)
BEGIN

IFCLR='1'THEN
COUNTER2<=0;
CLK_REG1<='0';
ELSIFCLK'EVENTANDCLK='0'THEN
IFCOUNTER2=N-1THEN
COUNTER2<=0;
CLK_REG1<=NOTCLK_REG;
ELSIFCOUNTER2=(N-1)/2THEN
COUNTER2<=COUNTER2+1;
CLK_REG1<=NOTCLK_REG1;
ELSE
COUNTER2<=COUNTER2+1;
ENDIF;
ENDIF;
ENDPROCESS;

CLKOUT<=CLK_REGORCLK_REG1;

ENDRTL;

 

loading...