FIR滤波器的四种实现方式及性能比较【VHDL+MATLAB】

EE323 DSD Project Report

Introduction:

In this project, we review the knowledge we learnt in the digital signal
process.

Then we use MATLAB to generate the filter coefficients and convert them into
binary. We use some added sin wave with different frequency to test our VHDL
project. We first use direct form and transposed form. Then we use algorithm
to optimize these forms. And compare the performance of different methods.

Task one:

1. Filter coefficients design:

Passband edge frequency 𝐹𝑝 and stopband edge frequency 𝐹𝑠 are specified in
Hz, along with sampling frequencies.

For S2:

2 ∗ 𝜋 ∗ 𝐹𝑝

𝜔𝑝 = 0.042𝜋 = 𝐹 ⇒ 𝐹

𝐹𝑝

= 0.021

𝑠𝑎𝑚𝑝𝑙𝑖𝑛𝑔

2 ∗ 𝜋 ∗ 𝐹𝑠

𝜔𝑠 = 0.14𝜋 =

𝑠𝑎𝑚𝑝𝑙𝑖𝑛𝑔

𝑠𝑎𝑚𝑝𝑙𝑖𝑛𝑔

𝐹𝑠

⇒

𝐹𝑠𝑎𝑚𝑝𝑙𝑖𝑛𝑔

= 0.07

𝛼𝑝 = −20 ∗ 𝑙𝑜𝑔10(1 − 𝛿𝑝) = 0.10486 𝑑𝐵

𝛼𝑠 = −20 ∗ 𝑙𝑜𝑔10(𝛿𝑠) = 60 𝑑𝐵

Then we can input these parameters into MATLAB and get the filter
coefficients. The magnitude response in 𝒅𝑩 scale was shown in this figure.
We can find that the filter can stratifies the conditions. In the passband,
we can find that the magnitude response is zero in 𝒅𝑩 scale which indicates
the signal with low frequency can pass easily. In the stopband, we can find
that the magnitude response is smaller than 60

in 𝒅𝑩 scale which indicates the signal with high frequency cannot pass
easily. Then we can take a look at the transition band, we can find the
slope of the transition band is steep.

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1. Waveform generation:

Then we can use MATLAB to generate test data to test the coefficients of
filter and the VHDL project. We need to generate two different frequency sin
wave and add them together. Then we need to quantize the output waveform and
convert it into binary.

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By these two figures, we can find that the coefficients of the filter are
correct, because the output waveform after the filter, the high frequency
components was filtered. Although the after filter waveform has some points
which are not perfect, the purpose of filter the high frequency components
has achieved.

1. Direct form:

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We had learnt some basic knowledge about filters in DSP. The direct form is
the most common filter form. It will cost N times multiplication and N-1
times addition. We also encountered some problems in the process of writing
the code. There are two main aspects, the first is the operation of
filtering wash. As the filtering coefficient contains decimal and negative
parts, it cannot be converted directly, and the coefficient must be
processed before the operation. The method we use here is the fixed-point
method of decimals. Since the decimal point is fixed, there is no need to
store it, so we can convert the decimal to an integer to perform operations.
We express fixed-point

decimals in binary terms. The highest bit is the sign bit, so it’s valid to
be 15 bits. Before we do that, we’re going to say that all data types are
signed. Since converting a fixed point decimal to a decimal results in
rounding and discarding the remaining decimal parts, this algorithm will
still have errors, but will be very small. The second problem is the
overflow problem in the calculation process. Due to the phenomenon of carry
in addition calculation, however, it is difficult to increase the number of
bits by loop during calculation because the same bits can only be added. In
this case, we use the method of resize to readjust each calculated binary
digit to include the overflow digit.

1. library IEEE;
2. use IEEE.STD_LOGIC_1164.ALL;
3. use ieee.numeric_std.all;
4.
5. entity dir_fir1 is
6. port(
7. clk : in std_logic;
8. reset : in std_logic;
9. data_In : in signed(11 downto 0);
10. data_Out : out std_logic_vector(15 downto 0)
11. );
12. end dir_fir1;
13.
14. architecture fir_bhv of dir_fir1 is
15. type array_1 is array(0 to 51) of signed(15 downto 0);
16. type array_2 is array(0 to 51) of signed(27 downto 0);
17. type array_3 is array(1 to 51) of signed(27 downto 0);
18. signal tap : array_1;
19. signal tap_sum : array_3;
20. signal tap_mul : array_2;
21. constant coef :array_1 := (to_signed(3,16),
22. to_signed(-33,16),
23. to_signed(-49,16),
24. to_signed(-75,16),
25. to_signed(-115,16),
26. to_signed(-154,16),
27. to_signed(-197,16),
28. to_signed(-236,16),
29. to_signed(-269,16),
30. to_signed(-282,16),
31. to_signed(-275,16),
32. to_signed(-236,16),
33. to_signed(-161,16),
34. to_signed(-46,16),
35. to_signed(115,16),
36. to_signed(318,16),
37. to_signed(560,16),
38. to_signed(836,16),
39. to_signed(1134,16),
40. to_signed(1442,16),
41. to_signed(1747,16),
42. to_signed(2032,16),
43. to_signed(2284,16),
44. to_signed(2484,16),
45. to_signed(2628,16),
46. to_signed(2700,16),
47. to_signed(2700,16),
48. to_signed(2628,16),
49. to_signed(2484,16),
50. to_signed(2284,16),
51. to_signed(2032,16),
52. to_signed(1747,16),
53. to_signed(1442,16),
54. to_signed(1134,16),
55. to_signed(836,16),
56. to_signed(560,16),
57. to_signed(318,16),
58. to_signed(115,16),
59. to_signed(-46,16),
60. to_signed(-161,16),
61. to_signed(-236,16),
62. to_signed(-275,16),
63. to_signed(-282,16),
64. to_signed(-269,16),
65. to_signed(-236,16),
66. to_signed(-197,16),
67. to_signed(-154,16),
68. to_signed(-115,16),
69. to_signed(-75,16),
70. to_signed(-49,16),
71. to_signed(-33,16),
72. to_signed(3,16));
73. begin
74. proc:process(Clk,Reset)
75. begin
76. if reset=‘1’ <