ARMv7-M provides an interrupt controller as an integral part of the ARMv7-M exception model.
ARMv7-M supports level-sensitivie and pulse-sensitive interrupt behavior.
Pulse interrupt sources must be held long enough to be sampled reliably by the processor clock to ensure they are lated and become pending. Pulses held for a clokc period act linke edge-sensitive interrupts. These can become pending again while the interrupt is active.
level-based interrupts becomes pending, and then make the interrupt active. The interrupt Service Routine then acesses the peripheral, causing it to seassert the interrupt. If the interrupt is still asserted on return from the ISR, it becomes pending again.
The NVIC supports the following features:
• NVIC interrupts can be enabled and disabled by writing to their corresponding
Interrupt Set-Enable or
Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current enabled state of the corresponding (32) interrupts.
When an interrupt is disabled, interrupt assertion causes the interrupt to become pending, but the interrupt cannot become active. If an interrupt is active when it is disabled, it remains in the active state until this is cleared by a reset or an exception return. Clearing the enable bit prevents any new activation of the associated interrupt.
An implementation can hard-wire interrupt enable bits to zero if the associated interrupt line does not exist, or hard-wired them to one if the associated interrupt line cannot be disabled.
• Software can set or remove the pending state of NVIC interrupts using a complementary pair of registers, the
Set-Pending Register and
Clear-Pending Register. The registers use a
write-one-to-enable and
write-one-to-clear policy, and a read of either register returns the current pending state of the corresponding 32 interrupts. Writing 1 to a bit in the Clear-Pending Register has no effect on the execution status of an active interrupt. It is IMPLEMENTATION DEFINED for each interrupt line supported, whether an interrupt supports either or both setting and clearing of the associated pending state under software control.
•
Active bit status is provided to enable software to determine whether an interrupt is inactive, active, pending,
or active and pending.
The following are registers related to NVIC.
Interrupt Controller Type register, ICTR
Purpose shows the
number of interrupt that the NVIC supports.