Timing Library Format (TLF)

TLF is an ASCII representation of the timing and power parameters associated with any cell in a particular semiconductor technology. The timing and power parameters are obtained by simulating the cells under a variety of conditions and the data is represented in the TLF format.

The TLF file contains timing models and data to calculate

• I/O delay paths
• Timing check values
• Interconnect delays

I/O path delays and timing check values are computed on a per-instance basis.

Path delays in a circuit depend upon the electrical behavior of interconnects between cells. This parasitic information can be based on the layout of the design, but must be estimated when no layout information is available.

And it is no possible to predict the process, voltage and temperature variations and derating factors can be included to compensate for these variations.

Cell-based Delay Calculation

Cell-based Delay Calculation is modeled by characterizing cell delay and output transition time (output slew) as a function of input transition time (input slew) and the capacitive load on the output of the cell.

Timing checks are also functions of  input slew and output and capacitive load.

Each cell has a specific number of input to output paths.

Path delays can be described for each input signal transition that affects an output signal.

The path delay can also depend on signals at other inputs (state dependencies).

In many sequential cells, the pat delay from an input pin to an output pin can depend on the path delay from another output pin to this output pin.

The TLF file is organized in twp scopes:

• Library Scope

Vendor and technology used

Global models for timing

Net resistance and capacitance(wireloads)

• Cell Scope

Cell definitions

Default values can be redifined for the cell

Information about every path in the cell and pin information

What we will have and not have in our library???

Library Scope

• Header information
• No wireload models:Prior design data is required to accurately generate these models. We will rather use tools like Cadence PKS or Synopsys Physical Compiler.
• Operation conditions, derating factors, limits and units: Three different values are usually required: typical, worst and best case. However, to accurately get these three values process parameters and transistors models for the entire process spread are required. This informatin is only available to the foundry. We can perform simulations only with MOSIS  provided models. Average extraction parameters and spice models will be used for the simulations. We can still run simulations at various temperatures and voltages. We can use +/- 5% or +/- 10% variations as best and worst case values. When using the library, keep in mind that you need to guard band for these variations.

proc_var( ) property

Specifies the reference points for process variation used for the characterization. Our file will contain values for only one process point and so a 1.0 will be used. However, we can create three different files for typical, worst and best.

temperature and voltage

Specifies the tempreatue and voltage reference points.

proc_mult ( ), temp_mult ( ) and volt_mult ( )

Multipliers that are used by the timing tools to derate data due to variations in process,  temperature and voltage.

table_input_theshold ( ), table_output_theshold ( ), table_transition_start ( ) and table_transition_end ( ).

Low and high threshold values for slew calculation (10% - 90% points) and the threshold for delay calculations (50% points).

slew_limit( ) and load_limit( )

Specifies the limits on maximum input slew on an input pin and the maximum output capacitance on any output pin

unit( )

Specifies the units used for time, capacitance, area, power, voltage etc.

Cell Scope

Cell(cell_name )
The cell name

Area( )
Specifies the cell area, used during logic synthesis and timing analysis (wireload)

TIMING_model(timing_arc_name)
Specifies the timing models to use for the particular path in the circuit
Three different models can be used