关于串并转换的VERILOG代码
关于串并转换的VERILOG代码
设计题目:
8位数据总线,能实现串行数据到8位并行数据的转换,以及8位并行数据到串行数据的转换.具体是哪种转换由sp控制端决定,当sp=1时,是串行输入/并行输出;当sp=0时,是并行输入/串行输出.
一,模块定义以及功能描述
输入端口 输入说明
rst 复位信号
clk 时钟信号
sp 使能信号
输出端口 输出说明
ack 连接应答信号
I/O端口 I/O说明
data 数据总线
二. 代码
1.功能模块部分
module ptosda(clk,rst,sp,dataack);
input clk,rst,sp;
inout ack;
input [7:0] data;
reg [3:0] state_out;
reg [7:0] databuf;
wire [7:0] data;
parameter bing=1'b0,
chuan=1'0;
parameter bit0=4'b0000,
bit1=4'b0001,
bit2=4'b0010,
bit3=4'b0011,
bit4=4'b0100,
bit5=4'b0101,
bit6=4'b0110,
bit7=4'b0111,
idel=4'b1000;
assign data[7]=link_write?databuf[7]:1'bz;
assign data=link_write?databuf:8'bz;
always@(posedge clk)
begin
if(!rst)
begin
ack <= 0;
link_write <=0;
state_out <= idle;
databuf <= 0;
end
else
begin
case(sp)
bing:
begin
if(finish_flag == 0)
begin
DtoS;
end
else
begin
state_out <= idel;
databuf <= data;
finish_flag = 0;
end
end
chuan:
begin
if(finish_flag == 0)
begin
StoD;
end
else
begin
state_out <= idel;
finish_flag = 0;
end
endcase
end
end
task StoD;
begin
case(state_out)
idle:
begin
link_write <= 0;
ack <= 1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit7;
end
bit7:
begin
ack <=1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit6;
end
bit6:
begin
ack <=1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit5;
end
bit5:
begin
ack <=1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit4;
end
bit4:
begin
ack <=1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit3;
end
bit2:
begin
ack <=1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit1;
end
bit1:
begin
ack<=1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit0;
end
bit0:
begin
link_write <= 1;
finish_flag=1;
ack <= 0;
state_out <= 4'b111;
end
default:
begin
link_write <= 0;
state_out <= 4'b111;
end
endcase
end
endtask
task DtoS;
begin
case(state_out)
idle:
begin
link_write <=1;
state_out <= bit7;
end
bit7:
begin
databuf <= databuf << 1;
state_out <= bit6;
end
bit6:
begin
databuf <= databuf << 1;
state_out <= bit5;
end
bit5:
begin
databuf <= databuf << 1;
state_out <= bit4;
end
bit4:
begin
databuf <= databuf << 1;
state_out <= bit3;
end
bit3:
begin
databuf <= databuf << 1;
state_out <= bit2;
end
bit2:
begin
databuf <= databuf << 1;
state_out <= bit1;
end
bit1:
begin
databuf <= databuf << 1;
state_out <= bit0;
end
bit0:
begin
link_write <= 0;
finish_flag = 1;
ack <= 1;
state_out <= 4'b1111;
end
default:
begin
link_write <= 0;
state_out <= 4'b1111;
end
endcase
end
endtask
endmodule
关于串并转换的VERILOG代码
设计题目:
8位数据总线,能实现串行数据到8位并行数据的转换,以及8位并行数据到串行数据的转换.具体是哪种转换由sp控制端决定,当sp=1时,是串行输入/并行输出;当sp=0时,是并行输入/串行输出.
一,模块定义以及功能描述
输入端口 输入说明
rst 复位信号
clk 时钟信号
sp 使能信号
输出端口 输出说明
ack 连接应答信号
I/O端口 I/O说明
data 数据总线
二. 代码
1.功能模块部分
module ptosda(clk,rst,sp,dataack);
input clk,rst,sp;
inout ack;
input [7:0] data;
reg [3:0] state_out;
reg [7:0] databuf;
wire [7:0] data;
parameter bing=1'b0,
chuan=1'0;
parameter bit0=4'b0000,
bit1=4'b0001,
bit2=4'b0010,
bit3=4'b0011,
bit4=4'b0100,
bit5=4'b0101,
bit6=4'b0110,
bit7=4'b0111,
idel=4'b1000;
assign data[7]=link_write?databuf[7]:1'bz;
assign data=link_write?databuf:8'bz;
always@(posedge clk)
begin
if(!rst)
begin
ack <= 0;
link_write <=0;
state_out <= idle;
databuf <= 0;
end
else
begin
case(sp)
bing:
begin
if(finish_flag == 0)
begin
DtoS;
end
else
begin
state_out <= idel;
databuf <= data;
finish_flag = 0;
end
end
chuan:
begin
if(finish_flag == 0)
begin
StoD;
end
else
begin
state_out <= idel;
finish_flag = 0;
end
endcase
end
end
task StoD;
begin
case(state_out)
idle:
begin
link_write <= 0;
ack <= 1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit7;
end
bit7:
begin
ack <=1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit6;
end
bit6:
begin
ack <=1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit5;
end
bit5:
begin
ack <=1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit4;
end
bit4:
begin
ack <=1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit3;
end
bit2:
begin
ack <=1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit1;
end
bit1:
begin
ack<=1;
databuf[7] <= data[7];
databuf <= databuf>>1;
state_out <= bit0;
end
bit0:
begin
link_write <= 1;
finish_flag=1;
ack <= 0;
state_out <= 4'b111;
end
default:
begin
link_write <= 0;
state_out <= 4'b111;
end
endcase
end
endtask
task DtoS;
begin
case(state_out)
idle:
begin
link_write <=1;
state_out <= bit7;
end
bit7:
begin
databuf <= databuf << 1;
state_out <= bit6;
end
bit6:
begin
databuf <= databuf << 1;
state_out <= bit5;
end
bit5:
begin
databuf <= databuf << 1;
state_out <= bit4;
end
bit4:
begin
databuf <= databuf << 1;
state_out <= bit3;
end
bit3:
begin
databuf <= databuf << 1;
state_out <= bit2;
end
bit2:
begin
databuf <= databuf << 1;
state_out <= bit1;
end
bit1:
begin
databuf <= databuf << 1;
state_out <= bit0;
end
bit0:
begin
link_write <= 0;
finish_flag = 1;
ack <= 1;
state_out <= 4'b1111;
end
default:
begin
link_write <= 0;
state_out <= 4'b1111;
end
endcase
end
endtask
endmodule