//五位并转串
module paraller2serial(
input clk,
input rst_n,
input [4:0] data_in,
input en,
output data_out
);
reg [4:0] data;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
data <=5'd0;
else if (en)
data <= data_in;
else
data <= data << 1;
end
assign data_out = data[4];
endmodule
并转串-Verilog
最新推荐文章于 2023-12-24 11:06:00 发布
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