并转串-Verilog

//五位并转串
module paraller2serial(
	input       clk,
	input       rst_n,
	input [4:0] data_in,
	input       en,
	output      data_out
    );
	 
	reg [4:0] data;
	
	always @ (posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			data <=5'd0;
		else if (en)
			data <= data_in;
		else
			data <= data << 1;			
	end

assign data_out = data[4];

endmodule