Chapter 25 Dynamic Analog Circuits
Dynamic analog circuits 利用了电容能存储电压信息的原理, 可以实现ample and holds, current mirrors, amplifiers, and filters 等功能
The MOSFET Switch
用NMOS做switch, 能传递最大电压为VDD-Vthn. 用PMOS做switch, 能传递最小电压为Vthp. 所以也可以用NMOS并联PMOS作为Transmission Gate (TG)
MOS switch有两个issue, charge injection and clock feedthrough
charge injection
gate由高变低, 一部分电荷注入到Cload, 引起Vout变化. 变化电压和Cload成反比.
Capacitive Feedthrough
当phi=gate signal升高, NMOS on Vout=Vin, Capacitive Feedthrough没影响
当phi=gate signal变低, NMOS off, A capacitive voltage divider exists between the gate-drain (source) capacitance and the load capacitance. 形成了vin-gate-vout的 capacitive voltage divider
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\Delta V_{load} =\frac{C_{overlap}\cdot VDD}{C_{overlap}+ C_{load}}
ΔVload=Coverlap+CloadCoverlap⋅VDD
Reduction of Charge Injection and Clock Feedthrough
为了减小上述效应, 一种最常用方法加dummy switch, 如上图所示M2. 注意M2的W/L size 只有M1的一半, 而且drain source shorted, M2 gate信号为M1 gate 信号phi的反向, in addition, should also be slightly delayed.
M1 off 时, 一半的channel charge注入到M2 (所以M2的size为M1的一半), M2 gate on吸收charge. 当M2 off时, It will inject half of its charge in both directions. 但是M1 on, M2的所有charge会注入到low-impedance 点也就是Vin, 不会影响到Vout.
还有一种解决charge Injection and Clock Feedthrough的方法 是采用CMOS transmission gate (TG). This results in lower changes in Vout because the complementary signals that are used will act to cancel each other. 因为PMOS和NMOS反向, 所以Vout变化较小. 但是TG需要精准的complementary clocks
方法三采用Fully-differential circuit
charge injection and clock feedthrough effects 表现为 common-mode signal to the amplifier, they will be reduced by the CMRR of the amplifier.
kT/C Noise
MOS作为switch, the maximum RMS output noise generated from a simple RC circuit was sqrt(kT/C).
Sample-and-Hold Circuits
switch的一个重要应用是sample-and-hold circuit, 其广泛应用于data converter applications.
上图是最简单的sample-and-hold电路, op-amp作为unity gain buffer. 在strobe signal on时, CH需要能charge到vin.
这个电路有clock feedthrough and charge injection的问题.
一种改进电路如下图所示, 两个op-amp buffer输入和输出.
S2 确保 amplifier A1 is stable in hold mode. 如果没有S2, A1的output在hold下将不受控, swing到rail上. S3确保在hold下, A1 disconnect.
这种结构有clock feedthrough and charge injection的问题. 另外During sample mode, 由于有两个op-amp, 系统可能不稳定, 需要注意compensation.
另外一种S/H 电路如下图所示
A control signal turns the transconductance amplifier A1 on and off, 因此就不需要S2和S3了.
第三种S/H电路如下图所示
注意到hold capacitor作为 A2 负反馈一部分.
当S1 off, any charge injected onto the hold capacitor results in a slight change in the
output voltage. 但是A2 输入为GND, the charge injection will be independent of the input signal and will result as a simple offset at the output. charge injection变成DC offset.
在Sample时, S1 on and S2 off. 等效电路为low-pass filter with buffered input.
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\frac{v_{out}}{v_{in}}=-\frac{R_{2}}{R_{1}}\cdot \frac{1}{(sR_{2}C_{H}+1)}
vinvout=−R1R2⋅(sR2CH+1)1
在hold时, vout=vin, while the switch S2 isolates the input from the hold capacitor. A2 需要为buffered op-amp因为接电阻负载.
由于在sample/hold时只接入一个op-amp, 所以这个电路比Fig 25.10的结构更容易稳定.
Fully-Differential Circuits
上面说到 用全差分运放可以减小switch的不良效应, 但是全差分运放需要用到common-mode-feedback (CMFB) 共模反馈电路.
Gain
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v_{out}=v_{op}-v_{om}=A_{OL}\cdot (v_{p}-v_{n})
vout=vop−vom=AOL⋅(vp−vn)
用于负反馈
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v_{p}\approx v_{n}
vp≈vn
Common-Mode Feedback (CMFB)
我们添加一个CMFB电路, 检测outputs of op-amp, 调整input, 确保output balanced around VCM(VDD/2).
Coupled Noise Rejection
Fully-Differential op-amps 可以抑制 input coupled noise (一般是common-mode)和power supply noise. 这样noise就传不到下一级了. For these reasons, that is, good coupled noise rejection and PSRR, the differential op-amp is a necessity in any dynamic analog integrated circuit.
Other Benefits of Fully-Differential Op-Amps
Fully-Differential op-amps可以doubling output voltage swing. VOP-VOM= -VDD ~ +VDD, range=2VDD.
Fully-Differentia还有一个好处就是input common-mode voltage of the op-amp 保持在VCM (由于CMFB). 因此第一级diff op-amp电压范围好满足.
A Fully-Differential Sample-and-Hold
t0-t1, amplifier 作为 unity gain buffer, 电路工作在sample mode.
At t1, ϕ 1 \phi1 ϕ1 switch off. charge injection and clock feedthrough作为input common-mode被reject. t1-t2, inputs of the op-amp = VOFF1+VCM. 时间要短
At t2, ϕ 2 \phi2 ϕ2 switch off. inputs of the op-amp = VOFF1+VOFF2+VCM. 时间要短
At t3, ϕ 3 \phi3 ϕ3 switch on. Op-amp 成为 voltage follower. inputs of the op-amp = VOFF1+VOFF2+VOFF3+VCM. 电路工作在hold mode
Connecting the Inputs to the Bottom (Poly1) Plate
注意CH电容下级板bottom plate应该接Vin signal而不是Op-amp input. 如果结成(b)这样, substrate的noise会直接影响op-amp的输入和输出. 另外substrate电容会增大setting time.
For these reasons, the parasitic capacitance on the top plate of the capacitor should be small.
Bottom Plate Sampling
ϕ 1 \phi1 ϕ1提前比 ϕ 2 \phi2 ϕ2关闭称为bottom plate sampling.
SPICE Simulation
Switched-Capacitor Circuits
switched-capacitor resistor, 如上图所示, ϕ 1 \phi1 ϕ1 和 ϕ 2 \phi2 ϕ2 nonoverlapping 交替开关, 形成一个大电阻, > 1Mohm.
利用q1=CV1, q2=CV2, q1-q2=C(V1-V2)=Iavg*Ts=(V1-V2)/R * Ts
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R_{sc}=\frac{1}{C\cdot f_{clk}}
Rsc=C⋅fclk1
可以用在RC filter中, 产生大的RC delay
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RC_{2}=\frac{C_{2}}{C1\cdot f_{clk}}
RC2=C1⋅fclkC2
注意, RC只和C2/C1的比例与fclk有关, C2/C1 ratio within 1%. 这样RC很准确.
最好把C1设加大, 大于寄生电容. 我们设计C1=1pf, fs=100KHz, C2=100pF. Reqv=10 Meg. 如果用CMOS的n-well做电阻会造成很大的error, 而且费面积.
Fig25.21a)的switched-capacitor resistor对寄生电容很敏感, 用处不太多, 考虑下图的switched-capacitor integrator.
S1-S4和CI构成switched-capacitor resistor:
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R_{sc}=\frac{1}{C_{I}\cdot f_{clk}}
Rsc=CI⋅fclk1
The transfer function of the switched-capacitor integrator: 注意Vin为负
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\frac{v_{out}}{v_{in}}=\frac{1/j\omega C_{F}}{R_{sc}}=\frac{1}{j\omega (\frac{C_{F}}{CI}\frac{1}{f_{clk}})}
vinvout=Rsc1/jωCF=jω(CICFfclk1)1
ratio of capacitor可以让designer精准控制amplifier的gain和integration time.
Parasitic Insensitive
上面结构对parasitic or stray capacitances不敏感. 因为op-amp的VN会hold在VCM.
Other Integrator Configurations
把 ϕ 1 \phi1 ϕ1和 ϕ 2 \phi2 ϕ2交换位置, 则Vout就反向
Fig25.25a:
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\frac{v_{out}}{v_{in}}=\frac{v_{1}}{j\omega(\frac{C_{F}}{C_{1}}\frac{1}{f_{clk}})}+\frac{v_{2}}{j\omega(\frac{C_{F}}{C_{2}}\frac{1}{f_{clk}})}-\frac{v_{3}}{j\omega(\frac{C_{F}}{C_{3}}\frac{1}{f_{clk}})}
vinvout=jω(C1CFfclk1)v1+jω(C2CFfclk1)v2−jω(C3CFfclk1)v3
注意V3输出反向
Fig25.25b 精简了管子, 另外添加了reset, 用来reset op-amp offset.
Fig. 25.26展示了lossy integrator (cap上并联一个resistor 用来 prevent the capacitor from storing charge due to offset currents and voltages at the input), 用于first-order filter design.
其transfer function如下所示, 另外也对寄生电容不敏感.
DC gain is 10 (20dB), we have
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\frac{C_{3}}{C_{4}}=10
C4C3=10
Pole and Zero:
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f_{p}=\frac{1}{2\pi \frac{C_{2}}{C_{4}}\cdot \frac{1}{f_{clk}}}=500
fp=2πC4C2⋅fclk11=500
f z = 1 2 π C 1 C 3 ⋅ 1 f c l k = 5 K H z f_{z}=\frac{1}{2\pi \frac{C_{1}}{C_{3}}\cdot \frac{1}{f_{clk}}}=5KHz fz=2πC3C1⋅fclk11=5KHz
Exact Frequency Response of a Switched-Capacitor Integrator
vout at time nT和(n+1)T
考虑delay
Capacitor Layout
cap的绝对值不太重要, 重要的是ratio. 用unity cell来做.
Op-Amp Settling Time
Closed-Loop gain:
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A_{CL}=\frac{A_{OL}}{1+A_{OL}\beta}
ACL=1+AOLβAOL
Open-Loop gain:
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A_{OL}=\frac{A_{OL}(0)}{1+j\frac{f}{f_{3dB}}}
AOL=1+jf3dBfAOL(0)
因此closed-loop gain:
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A_{CL}=\frac{\frac{1}{\beta}}{1+j\frac{f}{f_{un}\beta}}=\frac{\frac{1}{\beta}}{1+\frac{S}{\text{GBW}\cdot \beta}}
ACL=1+jfunβfβ1=1+GBW⋅βSβ1
f3db*AOL(0)=fun=GBW, 注意GBW和输出电容强相关.
closed loop low-frequency gain=1/beta.
定义time constant
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\tau=\frac{1}{2\pi f_{un}\cdot \beta}
τ=2πfun⋅β1
忽略slew-rate, op-amp输出为
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v_{out}=V_{outfinal}(1-e^{-t/\tau})
vout=Voutfinal(1−e−t/τ)
输出Vout达到稳态的1%的setting time需要5*tau. As rule of thumb的估算, setting time=1/(fun * beta)
settimg time
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\text{settimg time}=5\tau=\frac{5}{2\pi f_{un}\cdot \beta}\approx \frac{1}{f_{un}\beta}
settimg time=5τ=2πfun⋅β5≈funβ1
Circuits
Reducing Offset Voltage of an Op-Amp
解决思路就是用cap存储offset, 用来抵消Op-amp的offset.
phi1和phi2为nonoverlapping clock
Dynamic Comparator
对于b, 当A=V1时, B=GND, 当A=V2时, B floating. 因此
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V_{B}=(V_{2}-V_{1})\frac{C_{A}}{C_{A}+C_{B}}
VB=(V2−V1)CA+CBCA
当phi1=high, A=Vm, inverter input=output. (The inverter is operating as a linear amplifier where both M1 and M2 are in the saturation regions.)
当phi2=high, A=Vp, CA>>inverter input cap, 则voltage change on the input of the inverter (VB) is
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v_{in}=v_{p}-v_{m}
vin=vp−vm
The output is then latched and available during phi1. The gain of the comparator can be increased by using additional inverter stages.
利用input offset storage (IOS) or output offset storage (OOS)可以做高性能dynamic comparator
storage capacitors考虑三点: (1)preamp or latch input capacitance, (2) charge injection, and (3) kT/C noise
Dynamic Current Mirrors
dynamic techniques可以减小current mirror中Vth带来的mismatch.
当ph1=high, S1, S3 on, S2 off. 电流Iref流过M1, set M1 Vgs, 存储在C上.
当ph2=high, S1, S3 off, S2 on. 电流Iout流过M2,M1, Iout=Iref, neglecting channel length modulation.
下图展示dynamic current mirror that operates continuously.
phi1高, M2 sink current. phi2高, M1 sink current. 这个可以有效消除threshold voltage and transconductance不同带来电流不同.
Dynamic Amplifiers
当phi=low, dynamically biases M1 and M2, The circuit amplifies.
当phi=high. C1,C2远大于M1和M2的input cap, then the input AC signal, vin , is applied to both gates.
This biasing scheme makes the amplifier less sensitive to threshold and power supply variations. Dynamic Amplifiers还是有用的.
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