HDL—Verilog Language—Procedures—Always blocks（combinational）

赋值的时候既可以用assign也可以用always

但注意

assign 左边可以用wire型

always 内的用reg型

Build an AND gate using both an assign statement and a combinational always block. (Since assign statements and combinational always blocks function identically, there is no way to enforce that you're using both methods. But you're here for practice, right?...)

使用assign语句和always组合代码块构建AND门。(由于assign语句和combinational always语句的作用相同，因此没有办法强制你同时使用这两种方法。但你是来练习的，对吧?)

 // synthesis verilog_input_version verilog_2001
module top_module(
    input a,
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
    assign out_assign = a & b;
    always @(*) out_alwaysblock <= a & b;
endmodule