HDL—Verilog Language—Basics—7458 chips

The 7458 is a chip with four AND gates and two OR gates. This problem is slightly more complex than 7420.

7458是一款具有四个“与”门和两个“或”门的芯片。这个问题比7420稍微复杂一些。

Create a module with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an assign statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates. For extra practice, try it both ways.

创建一个与7458芯片具有相同功能的模块。它有10个输入和2个输出。您可以选择使用assign语句来驱动每条输出线，也可以选择声明（四条）线用作中间信号，其中每条内部线由其中一个AND门的输出驱动。对于额外的练习，可以双管齐下。

还是一样，看文字还是太复杂了，直接看图得了

首先看输入输出

输入：p1a-f p2a-d

输出：p1y p2y

看图片，p2a p2b用与门连起来，p2c p2d用与门连起来，两个的输出用或门连起来，值从p2y输出

assign p2y = (p2a & p2b)||(p2d & p2c);

p1a p1b p1c的输入用与门连起来，p1d p1e p1f的输入用与门连起来，之后将两个的输出用或门连起来，再从p1y输出

assign p1y = (p1a & p1b & p1c)||(p1d & p1e & p1f);

整个代码就是

module top_module (
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    assign p1y = (p1a & p1b & p1c)||(p1d & p1e & p1f);
    assign p2y = (p2a & p2b)||(p2d & p2c);
endmodule