dsPIC30F osc config

Dear all, 
I've been working with dsPIC30F for one year. But I'm not really familiar with their osc. config selection. I have some questions listed below: 
1). What is the difference between "_FOSC(CSW_FSCM_OFF & XT_PLL8);" and "_FOSC(CSW_FSCM_OFF & FRC & XT_PLL8);" and "_FOSC(CSW_FSCM_OFF & FRC & FRC_PLL8);"? 
2). I have some 6014s. I config them with some osc. configurations and the result is: 
"_FOSC(CSW_FSCM_OFF & FRC & FRC_PLL8);"  -----> run well. 
"_FOSC(CSW_FSCM_OFF & FRC & XT_PLL8);"    -----> run well. 
"_FOSC(CSW_FSCM_OFF & XT_PLL8);"              -----> not run!!! 
(there's already an 8MHz external crystal). 
  
I read carefully the datasheet and user's manual, but I really can not find out the answer. I worked with dsPIC30F4011, and there was no problem like this. 
Can someone give me an explaination? 
Thank you and hope to receive help from all of you. 
  
Kind regards, 

blackmoon. 

First,

CSW_FSCM_OFF

means clock switching and fail safe monitor are disabled. 

_FOSC(CSW_FSCM_OFF & XT_PLL8);

The crystal connected to OSC1/OSC2 is the clock source (8x PLL applied, primary oscillator). 

_FOSC(CSW_FSCM_OFF & FRC & XT_PLL8);

The internal FRC oscillator is the clock source. "XT_PLL8" is used as the primary oscillator, but this setting is meaningless, since clock switching is disabled (a clock switch to the primary oscillator would use the crystal as the clock source). 

_FOSC(CSW_FSCM_OFF & FRC & FRC_PLL8);

The 30F6014 doesn't provide a PLL option for the FRC. So I assume you're using a 30F6014 A . The internal FRC oscillator is the clock source (no PLL applied). Again, "FRC_PLL8" is meaningless, since no clock switch to the primary oscillator is possible. 

So, there is no difference between

_FOSC(CSW_FSCM_OFF & FRC & XT_PLL8);

and

_FOSC(CSW_FSCM_OFF & FRC & FRC_PLL8);

except the OSC2 pin function, which is determined by the primary oscillator setting (XT_PLL8 or FRC_PLL8). In the latter case OSC2 can be used as a general I/O pin (check the errata, whether this is true for your device or not). 

"_FOSC(CSW_FSCM_OFF & XT_PLL8);"            -----> not run!!!

It's a valid setting. If it doesn't work, there's perhaps something wrong in your crystal circuit (capacitor values, wiring, ...). 


Best regards, 
Bernd

Hi Bernd, 

Thank you very much for your answer. 
  
Now I understand from you that: 
"_FOSC(X&Y&Z);"  -----> Y = clock source, Z = second option for osc which allow us switch to in case clock source selected by Y does not work properly. Of course, Z is only meaning when X = clock switching is permited. 
  
Sorry but I really think Z is primary oscillator mode, and it is meaning when use clock source  = primary oscillator only, not affect FRC, EC or LPRC. For clock switching, there are two cases: 
The first is when clock failure is detected and Fail Safe Clock Monitoring is ON. In this case, clock source is switched over to internal FRC. 
The second case is when OSWEN bit in OSCCON register is set. In this case, clock source is switched to option selected by NOSC bits in that register. 
  
Am I right? 

About my problem with external crystal, I use 22pF caps and some values of crystal (7.3728M, 8M, 10M). I tried with 05 30F5013s and 03 30F6014s (without A suffix), crystal is placed closely enough to 30F. It's so sad that all of them could not run with external crystal. The date code of the chips are 04xxxxxx so I wonder there's some bugs in first versions or not. 

Kind regards, 
blackmoon. 

"_FOSC(X&Y&Z);"  -----> Y = clock source, Z = second option for osc

This is correct for any _FOSC statement with Y = LP, FRC or LPRC. Those settings change at least one of the <FOS1:FOS0> configuration bits from "1" to "0", but doesn't affect <FPR3:FPR0>. Z has to be of course one of the primary oscillator modes. 

All other oscillator mode settings (XT, EC, ...) belong to the primary group and leave <FOS1:FOS0> unaffected ("11") while changing the <FPR3:FPR0> configuration bits. 

While coming out of POR or BOR the <FOSC1:FOSC0> bits determine the clock source: 

11: one of the primary clock sources (determined by <FPR3:FPR0>) 
10: internal LPRC 
01: internal FRC 
00: secondary (LP) 

The first is when clock failure is detected and Fail Safe Clock Monitoring is ON. In this case, clock source is switched over to internal FRC.

Right. 

The second case is when OSWEN bit in OSCCON register is set. In this case, clock source is switched to option selected by NOSC bits in that register.

Yes. In this case, the <FPR3:FPR0> bits specify the clock source used when switching to the primary oscillator. 

About my problem with external crystal, I use 22pF caps and some values of crystal (7.3728M, 8M, 10M).

What's the recommended load capacitance for the crystals you are using? You may try larger values for the caps. 


Best regards, 
Bernd

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