EGo1下板_LED循环点亮

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项目源码：
链接：https://pan.baidu.com/s/10s2ncSJfKUnL13BAPKWDNg
提取码：1234

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20230605
补充下：
链接：https://pan.baidu.com/s/1kd_GDUkYB73toXYTutYzzw
提取码：4321

底下这个代码就是top_led_dynamic模块，和这篇博客的data_display连接一下就是全部代码
https://blog.csdn.net/Bunny9__/article/details/115048130

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题目介绍：
LED循环电路
使用开发板的4个数码管，通过将数据不断旋转和移动来显示更多的信息。例如，设计输入的信息是10位数（如“0123456789”），可以将其显示为“0123”、“1234”、“2345”、 … 、“7890”、“8901”。

1. 电路的输入信号en进行启用或暂停旋转，输入信号dir指定方向（向左或向右）；
2. 用案件控制循环，按一下显示一组数据。

1. 模块调用关系

2. 数据确定模块data_display

module data_display(
    output  reg     [3:0]   data3,
    output  reg     [3:0]   data2,
    output  reg     [3:0]   data1,
    output  reg     [3:0]   data0,
    
    input   wire            en,     // start or pause
    input   wire            dir,    // cycle direction
    input   wire            play,   // cycle once
    input   wire            rst    // reset
    );
    
    always @ (negedge rst or posedge play)  begin
        if (rst == 1'b0) begin
            data3   <=  4'h1;
            data2   <=  4'h2;
            data1   <=  4'h3;
            data0   <=  4'h4;
        end else begin
            if (en == 1'b1) begin
                if (dir == 1'b1) begin
                    data3   <=  (data3 + 1) % 10;
                    data2   <=  (data2 + 1) % 10;
                    data1   <=  (data1 + 1) % 10;
                    data0   <=  (data0 + 1) % 10;
                end else begin
                    data3   <=  (data3 + 9) % 10;
                    data2   <=  (data2 + 9) % 10;
                    data1   <=  (data1 + 9) % 10;
                    data0   <=  (data0 + 9) % 10;
                end
            end else begin
                data3   <=  data3;
                data2   <=  data2;
                data1   <=  data1;
                data0   <=  data0;
            end
        end
    
    end
    
    
endmodule

3. 约束文件

set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {an[3]}]
set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {an[2]}]
set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {an[1]}]
set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {an[0]}]

set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg[0]}]
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg[1]}]
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg[2]}]
set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg[3]}]
set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg[4]}]
set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg[5]}]
set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg[6]}]
set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg[7]}]

set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports clk_sys ]

set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {en}]
set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {dir}]
set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {rst}]
set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {play}]

4. 错误分析及解决

报错信息：

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets play_IBUF] >
play_IBUF_inst (IBUF.O) is locked to IOB_X1Y16
and play_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

[Place 30-99] Placer failed with error: ‘IO Clock Placer failed’
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

综合可以通过，实现报错
原因：在data_display模块中always的敏感信号用了除时钟以外的外部信号rst和play（这里用了板子的开关SW），因为Vivado在处理外部时钟信号的时候会自动添加BUFG模块来去除时钟的抖动，但是其他的信号就不会这样做，这样的话在always语句的敏感信号列表中使用没有去抖动的外部信号就有可能导致系统不稳定，所以会出现这个错误。
解决方法：在约束文件下多添加，这两句可以都加或者只加一条，不明白，暂缓

 //set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_IBUF] 
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets play] 
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst]