LPDDR4 Note--JEDEC-209-4B

• Applications shall ensure that ZQCal_Start commands to one rank on any dies sharing a ZQ resistor
must complete (tZQCal satisfied) prior to issuing a ZQCal_Start command to a different rank tied to the
resistor. (Applications can satisfy this requirement, for example, by either:
- Issuing ZQCal_Start commands simultaneously to both DRAM channels
- Issuing ZQCal_Start commands to one DRAM channel only)
• DRAM shall ensure that ZQCal_Start can be sent independently to the two channels on a die. If a
ZQCal_Start command is received while a ZQ calibration is in progress on the die, the second
ZQCal_Start command will be ignored and the in progress calibration will not be interrupted.

LPDDR4-SDRAM is a high-speed synchronous DRAM device internally configured with either 1 or 2 channels.

Each channel is comprised of 8-banks with from 2 Gb to 16 Gb per channel density. The configuration for channel density that is greater than 16Gb is still TBD.