Altera(Intel)时序约束文件SDC

##  SDC file "test.out.sdc"

## Copyright (C) 2016  Intel Corporation. All rights reserved.
## VENDOR  "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition"
## DATE    "Fri Sep 28 17:23:28 1999"
##
## DEVICE  "xxxxxxx"
##
#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3

#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]
create_clock -name {ext_clk} -period 18.519 -waveform { 0.000 9.260 } [get_ports { ext_clk }]
create_clock -name {mem_dqs[0]_IN} -period 4.629 -waveform { 0.000 2.315 } [get_ports {mem_dqs[0]}] -add

#**************************************************************
# Create Generated Clock
#**************************************************************

create_generated_clock -name {u_clock|u_pll|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} \
    -source [get_pins {u_clock|u_pll|general[0].gpll~FRACTIONAL_PLL|refclkin}] \
    -duty_cycle 50/1 -multiply_by 8 -master_clock {ext_clk} \
    [get_pins {u_clock|u_pll|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] 

create_generated_clock -name {u_clock|u_pll|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} \
    -source [get_pins {u_clock|u_pll|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] \
    -duty_cycle 50/1 -multiply_by 1 -divide_by 16 \
    -master_clock {u_clock|u_pll|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} \
    [get_pins {u_clock|u_pll|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 

#**************************************************************
# Set Clock Latency
#**************************************************************

#**************************************************************
# Set Clock Uncertainty
#**************************************************************

set_clock_uncertainty -rise_from [get_clocks {clk_1khz}] -rise_to [get_clocks {mem_dqs_n[3]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_1khz}] -fall_to [get_clocks {mem_dqs_n[3]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_1khz}] -rise_to [get_clocks {mem_dqs_n[2]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_1khz}] -fall_to [get_clocks {mem_dqs_n[2]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_1khz}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_1khz}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_1khz}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_1khz}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  

#**************************************************************
# Set Input Delay
#**************************************************************

set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.433 [get_ports {mem_dq[0]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.595 [get_ports {mem_dq[0]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.433 [get_ports {mem_dq[1]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.595 [get_ports {mem_dq[1]}]

#**************************************************************
# Set Output Delay
#**************************************************************

set_output_delay -add_delay -max -clock [get_clocks {mem_ck_n}]  0.840 [get_ports {mem_ca[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck_n}]  -0.750 [get_ports {mem_ca[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck}]  0.840 [get_ports {mem_ca[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck}]  -0.750 [get_ports {mem_ca[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck_n}]  0.840 [get_ports {mem_ca[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck_n}]  -0.750 [get_ports {mem_ca[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck}]  0.840 [get_ports {mem_ca[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck}]  -0.750 [get_ports {mem_ca[1]}]

#**************************************************************
# Set Clock Groups
#**************************************************************

set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
set_clock_groups -physically_exclusive -group [get_clocks {mem_dqs[0]_IN}] -group [get_clocks {mem_dqs[0]_OUT mem_dqs_n[0]_OUT}] 
set_clock_groups -physically_exclusive -group [get_clocks {mem_dqs[1]_IN}] -group [get_clocks {mem_dqs[1]_OUT mem_dqs_n[1]_OUT}] 
set_clock_groups -physically_exclusive -group [get_clocks {mem_dqs[2]_IN}] -group [get_clocks {mem_dqs[2]_OUT mem_dqs_n[2]_OUT}] 
set_clock_groups -physically_exclusive -group [get_clocks {mem_dqs[3]_IN}] -group [get_clocks {mem_dqs[3]_OUT mem_dqs_n[3]_OUT}] 

#**************************************************************
# Set False Path
#**************************************************************

set_false_path  -fall_from  [get_clocks {u_mem|u_lpddr2|mem_if_lpddr2_emif_0|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk}]  -to  [get_clocks {mem_ck}]
set_false_path  -from  [get_clocks {u_mem|u_lpddr2|mem_if_lpddr2_emif_0|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}]  -to  [get_clocks {mem_dqs[0]_IN}]
set_false_path  -from  [get_clocks {u_mem|u_lpddr2|mem_if_lpddr2_emif_0|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}]  -to  [get_clocks {mem_dqs[1]_IN}]

#**************************************************************
# Set Multicycle Path
#**************************************************************

set_multicycle_path -setup -end -from  [get_clocks {u_mem|u_lpddr2|mem_if_lpddr2_emif_0|lpddr2_mem_if_lpddr2_emif_0_p0_sampling_clock}]  -to  [get_clocks *] 2
set_multicycle_path -hold -end -from  [get_clocks {u_mem|u_lpddr2|mem_if_lpddr2_emif_0|lpddr2_mem_if_lpddr2_emif_0_p0_sampling_clock}]  -to  [get_clocks *] 2

#**************************************************************
# Set Maximum Delay
#**************************************************************

set_max_delay -from [get_ports {mem_dq[0]}] -to [get_keepers {{*:u_mem|*:u_lpddr2|*:mem_if_lpddr2_emif_0|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:u_mem|*:u_lpddr2|*:mem_if_lpddr2_emif_0|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[1]}] -to [get_keepers {{*:u_mem|*:u_lpddr2|*:mem_if_lpddr2_emif_0|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:u_mem|*:u_lpddr2|*:mem_if_lpddr2_emif_0|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000

#**************************************************************
# Set Minimum Delay
#**************************************************************

set_min_delay -from [get_ports {mem_dq[0]}] -to [get_keepers {{*:u_mem|*:u_lpddr2|*:mem_if_lpddr2_emif_0|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:u_mem|*:u_lpddr2|*:mem_if_lpddr2_emif_0|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -2.315
set_min_delay -from [get_ports {mem_dq[1]}] -to [get_keepers {{*:u_mem|*:u_lpddr2|*:mem_if_lpddr2_emif_0|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:u_mem|*:u_lpddr2|*:mem_if_lpddr2_emif_0|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -2.315

#**************************************************************
# Set Input Transition
#**************************************************************